Nonvolatile semiconductor memory device and method of manufacturing the same

ABSTRACT

A nonvolatile semiconductor memory device includes an n-type region which is in contact with n +  drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n +  drain diffusion region, n-type region and p +  impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a nonvolatile semiconductormemory device and a method of manufacturing the same, and in particularto a so-called flash memory, i.e., an EEPROM (electrically Erasable andProgrammable Read Only Memory) allowing electrical erasing and writingof information, and a method of manufacturing the same.

[0003] 2. Description of the Background Art

[0004] EEPROMs have been known as a kind of nonvolatile semiconductormemory devices which allow free programming of data and also allowelectrical writing and erasing of information. Although the EEPROM hasan advantage that both writing and erasing can be executed electrically,it requires two transistors, i.e., a select transistor and a memorytransistor for each memory cell, so that integration to a higher degreeis difficult. In view of this, there has been proposed a flash EEPROM,in which each memory cell is formed of one transistor, and entirewritten information charges can be electrically erased at a time. Thisis disclosed, for example, in U.S. Pat. No. 4,868,619.

[0005]FIG. 81 is a block diagram showing a general structure of a flashmemory. Referring to FIG. 81, the structure includes a memory cellmatrix 100, an X-address decoder 200, a Y-gate 300, a Y-address decoder400, an address buffer 500, a write circuit 600, a sense amplifier 700,an I/O buffer 800 and a control logic 900.

[0006] Memory cell matrix 100 includes a plurality of memory transistorsarranged in a matrix form. Memory matrix 100 is connected to X-addressdecoder 200 and Y-gate 300. X-address decoder 200 and Y-gate 300function to select rows and columns in memory cell matrix 100,respectively. Y-gate 300 is connected to Y-address decoder 400.Y-address decoder 400 functions to provide information for selectingcolumns. X-address decoder 200 and Y-address decoder 400 are connectedto address buffer 500. Address buffer 500 functions to store temporarilyaddress information.

[0007] Y-gate 300 is connected to write circuit 600 and sense amplifier700. Write circuit 600 functions to perform writing during datainputting. Sense amplifier 700 functions to determine “0” or “1” as avalue of a current which flows during data outputting. Write circuit 600and sense amplifier 700 each are connected to I/O buffer 800. I/O buffer800 functions to store temporarily input/output data.

[0008] Address buffer 500 and I/O buffer 800 are connected to controllogic 900. Control logic 900 functions to control the operation of flashmemory. Control logic 900 performs control based on a chip enable signal/CE, an output enable signal /OE and a program signal. Characters “/” inreference characters such as “/CE” mean inversion.

[0009]FIG. 82 is an equivalent circuit diagram showing a schematicstructure of memory cell matrix 100 shown in FIG. 81. Referring to FIG.82, memory cell matrix 100 is provided with a plurality of word linesWL₁, WL₂ . . . , WL_(i) and a plurality of bit lines BL₁, BL₂ . . . ,BL_(i)which extends perpendicularly to each other to form a matrix. Theplurality of word lines WL₁ WL₂ . . . , WL_(i) are connected toX-address decoder 200 and are disposed in the row direction. Theplurality of bit lines BL₁ BL₂ . . . , BL_(i) are connected to Y-gate300 and are disposed in the column direction.

[0010] Memory transistors Q₁₁, Q₁₂, . . . , Q_(ij) are arranged atcrossings of the word lines and bit lines, respectively. Each memorytransistor has a drain connected to the corresponding bit line. Acontrol gate of each memory transistor is connected to the correspondingword line. A source of each memory transistor is connected to thecorresponding source line S_(i), S₂ . . . , S_(i) The sources of memorytransistors belonging to the same row are mutually connected.

[0011] A structure of each memory transistor forming the conventionalflash memory will now be described below.

[0012]FIG. 83 is a fragmentary plan showing a schematic structure ofmemory cell matrix 100 of the conventional flash memory. FIG. 84 is across section taken along line D-D′ in FIG. 83.

[0013] Referring mainly to FIG. 84, a p-type silicon substrate 1 isprovided at its main surface with drain diffusion regions 13 and asource diffusion region 12 which are spaced from each other with channelregions 2 therebetween, respectively. A floating gate electrode 4 isformed on each channel region 2 with a thin oxide film 3 of about 100 Åin thickness therebetween. A control gate electrode 6 is formed onfloating gate electrode 4 with an interlayer insulating film 5therebetween. Floating gate electrode 4 and control gate electrode 6 aremade of polycrystalline silicon doped with impurity, which will bereferred to as “doped polycrystalline silicon” hereinafter. A thermaloxide film 51 is formed over p-type silicon substrate 1, floating gateelectrode 4 and control gate electrode 6. A smooth coat film 8 made of,e.g., an oxide film is formed over floating gate electrode 4 and controlgate electrode 6.

[0014] Smooth coat film 8 is provided with a contact hole 9 reaching aportion of a surface of source diffusion region 12. A bit line 52, whichhas a portion electrically connected to source diffusion region 12through contact hole 19, extends on smooth coat film 8.

[0015] Referring mainly to FIG. 83, the plurality of word lines 6 arearranged perpendicularly to the plurality of bit lines 52. Each wordline 6 is integral with the plurality of control gate electrodes 6. Ateach of crossings of word lines 6 and bit lines 52, there is formedfloating gate electrode 4 located under control gate electrode 6. Thereare also formed element isolating oxide films 53, each of which isformed between two areas each including two floating gate electrodes 4neighboring to each other in the column direction.

[0016] Referring to FIG. 85, description will be given on a writeoperation of a flash EEPROM utilizing channel hot electrons. A voltageV_(D1) of about 6 to 8V is applied to drain diffusion region 13, and avoltage V_(G1) of about 10 to 15V is applied to control gate electrode6. Voltages V_(D1) and V_(G1) thus applied generate a large amount ofhigh energy electrons near drain diffusion region 13 and oxide film 3.The electrons thus generated are partially introduced into floating gateelectrode 4. Since the electrons are accumulated in floating gateelectrode 4 in this manner, a threshold voltage V_(TH) of the memorytransistor increases. The state where threshold voltage V_(TH) is higherthan a predetermined value is a written state and is called a “0” state.

[0017] Referring to FIG. 86, an erase operation utilizing an F-N(Fowler-Nordheim) tunnel phenomenon will be described below. A voltageV_(s) of about 10 to 12V is applied to source diffusion region 12,control gate electrode 6 is set to the ground potential, and draindiffusion region 13 is held at the floating state. Voltage V_(S) appliedto source diffusion region 12 generates an electric field, which causesthe F-N tunnel phenomenon to move electrons from floating gate electrode4 through thin oxide film 3. Since electrons are removed from floatinggate electrode 4, threshold voltage V_(TH) of the memory transistorlowers. The state where threshold voltage V_(TH) is lower than thepredetermined value is an erased state and is called an “1” state.

[0018] In a read operation, a voltage V_(G2) of about 5V is applied tocontrol gate electrode 6 shown in FIG. 84, and a voltage V_(D2) of about1 to 2V is applied to drain diffusion region 13. The foregoingdetermination of “1” or “0” is performed based on whether a currentflows through the channel region of memory transistor, i.e., whether thememory transistor is on or off. Thereby, information is read.

[0019] For the flash memory described above, there has been proposed adrain structure (which will be referred to as a “pocket structure”)shown in FIGS. 87 and 88 in order to improve write characteristics. FIG.88 shows, on an enlarged scale, a region S in FIG. 87.

[0020] A structure shown in FIGS. 87 and 88 is provided with a p-typepocket region 15 which is in contact with drain diffusion region 13 andcovers the periphery of the same. p-type pocket region 15 has animpurity concentration higher than that of the p-type silicon substrate.This raises an electric field at a drain end (region T in FIG. 88) in apn junction (formed of drain diffusion region 13 and pocket region 15)as shown in FIG. 89.

[0021]FIG. 89 shows electric fields in a direction parallel to eachchannel along line F-F′ in FIG. 88. More specifically, FIG. 89 shows at(a) the electric field in a structure not provided with the pocketregion, and shows at (b) the electric field in a structure provided withthe pocket region.

[0022] Provision of the pocket structure increases a rate of electronshaving a high energy in all electrons running through the channel. Thispromotes introduction or injection of electrons into the gate, and thusincreases the gate current.

[0023] As is apparent from the above, the pocket structure is employedfor improving the write characteristics by increasing the absolutequantity of channel hot electrons.

[0024] By employing the pocket structure, the electric field (Ex)parallel to the channel can be enhanced at the drain end as describedabove, and a probability of generation of high energy electrons can beimproved.

[0025] However, generated high energy electrons move toward the drain.In order to inject the high energy electrons into the floating gateelectrode, therefore, it is necessary to change the moving direction sothat the high energy electrons may be directed toward the floating gateelectrode by elastic scattering. However, electrons are randomlydirected by elastic collision with impurity 60 as shown in FIG. 90.Therefore, only a part of electrons have a moment in the floating gateelectrode direction, i.e., moment directed toward the floating gateelectrode.

[0026] Since the electric field along the gate electrode direction in abulk is low at a region where channel hot electrons generate, theprobability that high energy electrons have the moment in the gateelectrode direction after elastic collision is disadvantageously low.

[0027] In the pocket structure (FIGS. 87 and 88) described above, theelectric field (longitudinal electric field) in a vertical directionwith respect to the channel of insulating film 3 increases at the drainend where the most high energy electrons are generated. It is definedthat an arrival probability is a probability that generated high energyelectrons arrive at the floating gate. In this case, the longitudinalelectric field in insulating film 3 acts to reduce the arrivalprobability by the following reason.

[0028] First, under the application condition that drain voltage Vd issmaller than gate voltage Vg, the longitudinal electric field and thelateral electric field (i.e., electric field parallel to the channel) inthe insulating film 3 are distributed at the drain end as shown in FIG.91. Referring to FIG. 91, the most high energy electrons generate near apoint where the lateral electric field attains the highest value.However, the nearly maximum longitudinal electric field also generatesat the point where the maximum lateral electric field generates. As thelongitudinal electric field is larger, more electrons are forced toreturn toward the substrate, resulting in lowering of the probabilitythat high energy electrons are injected into the floating gateelectrode.

[0029] In the pocket structure described above, a majority of channelhot electrons generate at the drain end. As shown in FIG. 91, however,the drain end is a region at which the longitudinal electric fieldincreases, and in other words, is a region at which a large forcegenerates to return the injected electrons in the floating gateelectrode toward the substrate. Therefore, the pocket structure cannotbe considered as the structure which allows the generated hot electronsto be injected efficiently into the floating gate electrode.

[0030]FIG. 92B shows change in potential distribution along the verticaldirection (line E-E′ in FIG. 92A) with respect to the channel at thedrain end shown in FIG. 92A. Under the condition that drain voltage Vdis smaller than gate voltage Vg, a potential difference at theinsulating film 3 increases as the longitudinal electric field at theinsulating film 3 increases. Therefore, increase of the longitudinalelectric field at the insulating film 3 results in increase in height ofthe potential barrier of insulating film 3 over which electrons mustmove, as shown in FIG. 93. The electrons must have energies of amagnitude which allows them to move over at least the barrier ofinsulating film 3 in order to allow injection of electrons into thefloating gate electrode. Therefore, as the longitudinal electric fieldat insulating film 3 (i.e., height of the barrier of insulating film 3)increases, a rate of electrons having energies allowing movement overthe barrier of insulating film 3 decreases, provided that the generatedelectrons always have the same high energy. It can be considered fromthe foregoing that the arrival probability is restricted to a low valuein the pocket structure in which both of lateral and longitudinalelectric fields increase at the drain end.

[0031] As described above, the conventional pocket structure suffersfrom a problem that the longitudinal electric field is high at the pointwhere the maximum lateral electric field generates and the most hotelectrons are produced, so that the generated high energy electronscannot be injected into the floating gate with a high probability.

SUMMARY OF THE INVENTION

[0032] Accordingly, an object of the invention is to provide anonvolatile semiconductor memory device and a method of manufacturingthe same, in which an electric field along a gate electrode direction ina bulk is enhanced at a region where channel hot electrons generate soas to increase a probability with which high energy electrons afterelastic collision have a moment along the gate electrode direction.

[0033] Another object of the invention is to provide a nonvolatilesemiconductor memory device and a method of manufacturing the same, inwhich a longitudinal electric field is reduced at a point where alateral electric field has a peak and the most hot electrons generate soas to increase a probability with which generated high energy electronsare injected into a floating gate electrode.

[0034] According to an aspect of the invention, a nonvolatilesemiconductor memory device allowing electrical erasing and writing ofdata includes a semiconductor substrate of a first conductivity type, acharge accumulating electrode layer, a control electrode layer, a pairof source/drain regions of a second conductivity type, a first impurityregion of the second conductivity type, and a second impurity region ofthe first conductivity type. The semiconductor substrate has a mainsurface. The charge accumulating electrode layer is formed on the mainsurface of the semiconductor substrate with a first insulating filmtherebetween. The control electrode layer is formed on the chargeaccumulating electrode layer with a second insulating film therebetween.The pair of source/drain regions are formed at the main surface of thesemiconductor substrate and are located at opposite sides of a region ofthe semiconductor substrate located under the charge accumulatingelectrode layer. The drain region extends to a region of thesemiconductor substrate located immediately under the chargeaccumulating electrode layer. The first impurity region is located to bein contact with the drain region, and to have an impurity concentrationlower than that of the drain region at the main surface of thesemiconductor substrate located immediately under the chargeaccumulating electrode layer. The second impurity region is formed beingin contact with the first impurity region at the main surface of thesemiconductor substrate located immediately under the chargeaccumulating electrode layer, and has an impurity concentration higherthan that of the semiconductor substrate.

[0035] In the nonvolatile semiconductor memory device according to theabove aspect of the invention, the first impurity region of the secondconductivity type having the impurity concentration smaller than that ofthe drain region is arranged between the drain region and the secondimpurity region forming a pocket region. Therefore, a point where alateral electric field of the first insulating film can be shifted to aninterface between the first and second impurity regions. Accordingly, itis possible to reduce a longitudinal electric field at a point of themaximum lateral electric field, as compared with the prior art. Thisreduces a force returning electrons in the first insulating film towardthe substrate, and also reduces a height of an insulating film barrierover which electrons are to move, so that it is possible to increase aprobability of arrival of high energy electrons to the chargeaccumulating electrode (floating gate electrode), and thus a gatecurrent can be increased.

[0036] According to the above structure, the gate current can beincreased without considerably increasing the impurity concentration ofthe second impurity region forming the pocket region. Therefore, it ispossible to suppress a leak current between the diffusion region and thesubstrate, which may increase due to increase of the impurityconcentration of the second impurity region, and thus the writecapability can be improved.

[0037] Further, in the above structure, the gate current is increased byimproving the injection efficiency, so that the write capability can beimproved without increasing an electric field to be applied. Whenconsideration is made based on the write capability, this structure canbe operated with a low applied voltage. Therefore, this structure can beadvantageously employed in a low-voltage operation element and asingle-power-supply element.

[0038] Preferably, the device of the above aspect further includes athird impurity region of the first conductivity type coveringperipheries of the source region and the second impurity region whilebeing in contact with the source region and the second impurity region,and having an impurity concentration higher than that of thesemiconductor substrate and lower than that of the second impurityregion.

[0039] Since the third impurity region of the first conductivity typehaving the impurity concentration higher than that of the semiconductorsubstrate is formed at the main surface of the semiconductor substratelocated between the source region and the drain region, punch-throughcan be prevented. Therefore, a limit gate length determined in view ofan off breakdown voltage can be suppressed at a low value. Thus, thestructure is advantageous for fabrication of microscopic devices.

[0040] In addition to the third impurity region, the second impurityregion having the impurity concentration higher than that of the thirdimpurity region is formed at the main surface of the semiconductorsubstrate between the source and drain regions. This prevents thepunch-through further effectively.

[0041] By appropriately selecting the impurity concentrations of thesecond and third impurity regions, a threshold voltage can be controlledwhile maintaining an intended limit gate length and an intended writecapability.

[0042] Further, by appropriately selecting the impurity concentrationsof the second and third impurity regions, the impurity concentration ofthe second impurity region forming the pocket region can be reducedwhile maintaining an intended write capability and an intended thresholdvoltage. Therefore, the write capability can be improved withoutincreasing the leak current between the diffusion region and thesubstrate.

[0043] Preferably, the device of the above aspect further includes athird impurity region of the second conductivity type formed in thedrain region and having an impurity concentration higher than that ofthe drain region.

[0044] Preferably, the device of the above aspect further includes athird impurity region of said second conductivity type formed in thesource region and having an impurity concentration higher than that ofthe source region.

[0045] Preferably, the device of the above aspect further includes athird impurity region of the second conductivity type formed in thedrain region and having an impurity concentration higher than that ofthe drain region, and a fourth impurity region of said secondconductivity type formed in the source region and having an impurityconcentration higher than that of the source region.

[0046] Since the third impurity region(s) having the impurityconcentration higher than those of the drain region and/or source regionare formed at the drain region and/or source region, a parasiticresistance(s) of the drain region and/or source region can be reduced.Therefore, the current drive capability is increased, and thusimprovement of the write capability and increase of the read speed canbe expected.

[0047] Preferably, in the above aspect, a depth of the second impurityregion from the main surface of the semiconductor substrate is smallerthan that of the first impurity region.

[0048] Since the second impurity region is shallower than the firstimpurity region, an area through which the first and second impurityregions are in contact with each other can be small. Therefore, ajunction leak current between the diffusion region and the substrate canbe small, so that the voltage can be raised to a predetermined value,and a boost capability can be improved. Since the junction leak currentcan be small, the leak current of each of memory cells connected to wordlines can be small, so that a sum of the leak currents per block may besmall. Therefore, increase in number of the transistors per block can beexpected.

[0049] Preferably, in the above aspect, the second impurity region isformed to cover a periphery of the first impurity region while being incontact with the first impurity region.

[0050] Since the second impurity region having the impurityconcentration higher than that of the semiconductor substrate covers thefirst impurity region of the opposite conductivity type, a current whichmay cause the punch through can be reduced. Therefore, the channellength can be reduced, and shrinkage of the device is allowed.

[0051] Preferably, in the above aspect, the second and first impurityregions have the substantially equal depths from the main surface of thesemiconductor substrate.

[0052] Since the second and first impurity regions have thesubstantially equal depths, an area through which the second and firstimpurity regions are in contact with each other can be small, so that ajunction leak current between the diffusion region and the substrate canbe small. Further, a current caused by punch through can be reduced.

[0053] Preferably, in the above aspect, the device further includes athird impurity region covering a periphery of the source region whilebeing in contact with the source region, extending to a regionimmediately under the charge accumulating electrode layer, and having animpurity concentration lower than that of the source region.

[0054] Since the third impurity region having the impurity concentrationsmaller than that of the source region covers the source region, thispromote extension of a depletion layer at the source side duringoperation of the memory transistor, and thus the source breakdownvoltage increases. For example, when erasing (removal of electrons fromthe charge accumulating electrode layer) is performed at the source sideusing an F-N tunneling current, a high voltage can be applied to thesource. Preferably, in the above aspect, the second impurity region isformed to be in contact with the source region and the first impurityregion only at a region of the semiconductor substrate locatedimmediately under the charge accumulating electrode layer, and has animpurity concentration higher than that of the semiconductor substrate.

[0055] Since the second impurity region of the first conductivity typehaving the impurity concentration higher than that of the semiconductorsubstrate is arranged at the main surface of the semiconductor substratebetween the source region and the drain region, punch though can beprevented. Therefore, a limit gate length determined in view of an offbreakdown voltage can be suppressed at a low value. Thus, the structureis advantageous for fabrication of microscopic devices.

[0056] In the structure where the second impurity region is formed, forexample, only at a region immediately under the charge accumulatingelectrode layer, capacitances of the source and drain regions as well asa capacitance of the second impurity region are low. Therefore, increaseof the read speed can be expected.

[0057] Preferably, in the above aspect, a depth of the second impurityregion from the main surface of the semiconductor substrate is smallerthan that of the first impurity region.

[0058] Since the second impurity region is shallower than thesource/drain regions, it is possible to suppress variation of thethreshold voltage, which may be caused by variation of the substratepotential. Therefore, it is possible, for example, to suppress variationof an unfixed potential of a terminal in an open state.

[0059] According to further another aspect of the invention, anonvolatile semiconductor memory device allowing electrical erasing andwriting of data includes a semiconductor substrate of a firstconductivity type, a charge accumulating electrode layer, a controlelectrode layer, a pair of source/drain regions of a second conductivitytype, a first impurity region of the first conductivity type and asecond impurity region of the first conductivity type. The semiconductorsubstrate has a main surface. The charge accumulating electrode layer isformed on the main surface of the semiconductor substrate with a firstinsulating film therebetween. The control electrode layer is formed onthe charge accumulating electrode layer with a second insulating filmtherebetween. The pair of source/drain regions are formed at the mainsurface of the semiconductor substrate, and are located at oppositesides of a region of the semiconductor substrate under the chargeaccumulating electrode layer. The drain region extends to a region ofthe semiconductor substrate located immediately under the chargeaccumulating electrode layer, and contains impurity at a concentrationof 1×10²⁰cm⁻³ or more. The first impurity region covers a periphery ofthe drain region while it is in contact with the drain region, and hasan impurity concentration larger than that of the semiconductorsubstrate. The second impurity region is formed to be in contact withthe source region and the first impurity region at a region of thesemiconductor substrate located immediately under the chargeaccumulating electrode layer, and has an impurity concentration higherthan that of the semiconductor substrate and lower than that of thefirst impurity region.

[0060] According to the nonvolatile semiconductor memory device of theabove aspect of the invention, the drain region is covered with thefirst impurity region of the opposite conductivity type having theimpurity concentration larger than that of the semiconductor substrate.Therefore, an electric field along the gate electrode direction in thebulk increases, so that an efficiency of injection of high energyelectrons into the charge accumulating electrode layer is improved.Accordingly, the gate current increases, and the write capability can beimproved without increasing a voltage to be applied. By this reason, thestructure is advantageously employed in a low-voltage operating elementand a single-power-supply element.

[0061] Since the second impurity region of the first conductivity typehaving the impurity concentration higher than that of the semiconductorsubstrate is arranged at the main surface of the semiconductor substratebetween the source region and the drain region, punch though can beprevented. Therefore, a limit gate length determined in view of an offbreakdown voltage can be suppressed at a low value. Thus, the structureis advantageous for fabrication of microscopic devices.

[0062] In addition to the second impurity region, the first impurityregion having the impurity concentration higher than that of the secondimpurity region is arranged at the main surface of the semiconductorsubstrate between the source and drain regions. Therefore, the punchthrough can be prevented more effectively.

[0063] By appropriately selecting the impurity concentrations of thefirst and second impurity regions, a threshold voltage can be controlledwhile maintaining an intended limit gate length and an intended writecapability.

[0064] Further, by appropriately selecting the impurity concentrationsof the first and second impurity regions, the impurity concentration ofthe first impurity region can be reduced while maintaining an intendedwrite capability and an intended threshold voltage. Therefore, the writecapability can be improved without increasing the leak current betweenthe diffusion region and the substrate.

[0065] Preferably, in the above aspect, a depth of the second impurityregion from the main surface of the semiconductor substrate is smallerthan those of the source/drain regions.

[0066] Since the second impurity region is shallower than thesource/drain regions, it is possible to suppress variation of thethreshold voltage, which may be caused by variation of the substratepotential. Therefore, it is possible, for example, to suppress variationof an unfixed potential of a terminal in an open state.

[0067] Further, according to an aspect of the invention, a method ofmanufacturing a nonvolatile semiconductor memory device allowingelectrical erasing and writing of data includes the following steps:

[0068] First, a charge accumulating electrode layer is formed on a mainsurface of a semiconductor substrate of a first conductivity type with afirst insulating layer therebetween, and a control electrode layer isformed on the charge accumulating electrode layer with a secondinsulating film therebetween. A pair of source/drain regions of a secondconductivity type are formed at the main surface of the semiconductorsubstrate and are located at opposite sides of a region of thesemiconductor substrate located immediately under the chargeaccumulating electrode layer. The drain region extends to a region ofthe semiconductor substrate located immediately under the chargeaccumulating electrode layer. A first impurity region of a secondconductivity type having an impurity concentration lower than that ofthe drain region and being in contact with the drain region is formed atthe main surface of the semiconductor substrate located immediatelyunder the charge accumulating electrode layer. A second impurity regionof the first conductivity type having an impurity concentration higherthan that of the semiconductor substrate and being in contact with thefirst impurity region is formed at the main surface of the semiconductorsubstrate located immediately under the charge accumulating electrodelayer.

[0069] According to the above aspect of the invention, the method ofmanufacturing the nonvolatile semiconductor memory device can providethe nonvolatile semiconductor memory device in which high energyelectrons can be injected into the charge accumulating electrode layerwith a high injection efficiency.

[0070] According to another aspect of the invention, a method ofmanufacturing a nonvolatile semiconductor memory device allowingelectrical erasing and writing of data includes the following steps:

[0071] First, a charge accumulating electrode layer is formed on a mainsurface of a semiconductor substrate of a first conductivity type with afirst insulating layer therebetween, and a control electrode layer isformed on the charge accumulating electrode layer with a secondinsulating film therebetween. A pair of source/drain regions of a secondconductivity type are formed at the main surface of the semiconductorsubstrate and are located at opposite sides of a region of thesemiconductor substrate located immediately under the chargeaccumulating electrode layer. The drain region extends to a region ofthe semiconductor substrate located immediately under the chargeaccumulating electrode layer. A first impurity region of the secondconductivity type having an impurity concentration lower than that ofthe drain region and being in contact with the drain region is formed atthe main surface of the semiconductor substrate located immediatelyunder the charge accumulating electrode layer. A second impurity regionof the first conductivity type having an impurity concentration higherthan that of the semiconductor substrate and being in contact with thesource region and the first impurity region is formed at a region of thesemiconductor substrate located immediately under the chargeaccumulating electrode layer.

[0072] According to the above aspect of the invention, the method ofmanufacturing the nonvolatile semiconductor memory device can providethe nonvolatile semiconductor memory device in which high energyelectrons can be injected into the charge accumulating electrode layerwith a high injection efficiency.

[0073] According to still another aspect of the invention, a method ofmanufacturing a nonvolatile semiconductor memory device allowingelectrical erasing and writing of data includes the following steps:

[0074] A charge accumulating electrode layer is formed on a main surfaceof a semiconductor substrate of a first conductivity type with a firstinsulating layer therebetween, and a control electrode layer is formedon the charge accumulating electrode layer with a second insulating filmtherebetween. A pair of source/drain regions of the second conductivitytype are formed at the main surface of the semiconductor substrate andare located at opposite sides of a region of the semiconductor substratelocated immediately under the charge accumulating electrode layer. Thedrain region extends to a region of the semiconductor substrate locatedimmediately under the charge accumulating electrode layer, and has animpurity concentration of 1×10²⁰cm⁻³ or more. A first impurity region ofthe first conductivity type being in contact with the drain region,covering a periphery of the drain region and having an impurityconcentration larger than that of the semiconductor substrate is formed.A second impurity region of the first conductivity type having animpurity concentration larger than that of the semiconductor substrateand smaller than that of the first impurity region and being in contactwith the source region and the first impurity region is formed at aregion of the semiconductor substrate located immediately under thecharge accumulating electrode layer.

[0075] According to the above aspect of the invention, the method ofmanufacturing the nonvolatile semiconductor memory device can providethe nonvolatile semiconductor memory device in which high energyelectrons can be injected into the charge accumulating electrode layerwith a high injection efficiency.

[0076] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0077]FIG. 1 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 1 of theinvention;

[0078] FIGS. 2 to 14 are schematic cross sections showing, in accordancewith the order of steps, a method of manufacturing the nonvolatilesemiconductor memory device of the embodiment 1 of the invention;

[0079]FIG. 15 is a graph showing change of a lateral electric field ofan insulating film in accordance with change of an impurityconcentration of an n-type region;

[0080]FIG. 16 shows change of a lateral electric field of an insulatingfilm in structures provided with the n-type region and not provided withthe same;

[0081]FIG. 17 is a fragmentary cross section of a conventional structurefor showing a structure of a specimen used in simulation;

[0082]FIG. 18 is a fragmentary cross section of a structure of theinvention for showing a structure of a specimen used in simulation;

[0083]FIG. 19 is a graph showing an impurity concentration at variouspositions on line A-A′ in FIG. 17 and an electric field of an insulatingfilm corresponding to these positions;

[0084]FIG. 20 is a graph showing an impurity concentration at variouspositions on line A-A′ in FIG. 18 and an electric field of theinsulating film corresponding to these positions;

[0085]FIG. 21 is a graph showing an electric fields at various positionsof specimens of the prior art and the embodiment of the invention;

[0086]FIG. 22 is a graph showing relationships between a gate voltageand an injection efficiency of the prior art and the embodiment of theinvention;

[0087]FIG. 23 is a graph showing relationships between a leak currentand a maximum gate current of the prior art and the embodiment of theinvention;

[0088]FIG. 24 is a schematic cross section showing a conventional LDDstructure disclosed in a prior art reference;

[0089]FIG. 25 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 2 of theinvention;

[0090] FIGS. 26 to 30 are schematic cross sections showing, inaccordance with the order of steps, a method of manufacturing thenonvolatile semiconductor memory device of the embodiment 2 of theinvention;

[0091]FIG. 31 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 3 of theinvention;

[0092] FIGS. 32 to 36 are schematic cross sections showing, inaccordance with the order of steps, a method of manufacturing thenonvolatile semiconductor memory device of the embodiment 3 of theinvention;

[0093]FIG. 37 shows a sum of charges in a certain space;

[0094]FIG. 38 is a schematic cross section showing a structure of aconventional MOS transistor;

[0095]FIG. 39 shows distribution of a potential along line B-B′ in FIG.38;

[0096]FIG. 40 shows the same potential distribution as that in FIG. 39together with coordinates;

[0097]FIG. 41 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 4 of theinvention;

[0098] FIGS. 42 to 47 are schematic cross sections showing, inaccordance with the order of steps, a method of manufacturing thenonvolatile semiconductor memory device of the embodiment 4 of theinvention;

[0099]FIG. 48 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 5 of theinvention;

[0100] FIGS. 49 to 52 are schematic cross sections showing, inaccordance with the order of steps, a method of manufacturing thenonvolatile semiconductor memory device of the embodiment 5 of theinvention;

[0101]FIG. 53 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 6 of theinvention;

[0102] FIGS. 54 to 57 are schematic cross sections showing, inaccordance with the order of steps, a method of manufacturing thenonvolatile semiconductor memory device of the embodiment 6 of theinvention;

[0103]FIG. 58 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 7 of theinvention;

[0104]FIGS. 59 and 60 are schematic cross sections showing, inaccordance with the order of steps, a method of manufacturing thenonvolatile semiconductor memory device of the embodiment 7 of theinvention;

[0105]FIG. 61 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 8 of theinvention;

[0106]FIG. 62 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 9 of theinvention;

[0107]FIG. 63 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 10 of theinvention;

[0108]FIG. 64 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 11 of theinvention;

[0109]FIGS. 65 and 66 are schematic cross sections showing, inaccordance with the order of steps, a method of manufacturing thenonvolatile semiconductor memory device of the embodiment 11 of theinvention;

[0110]FIG. 67 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 12 of theinvention;

[0111]FIG. 68 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 13 of theinvention;

[0112]FIG. 69 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 14 of theinvention;

[0113]FIGS. 70 and 71 are schematic cross sections showing, inaccordance with the order of steps, a method of manufacturing thenonvolatile semiconductor memory device of the embodiment 14 of theinvention;

[0114]FIG. 72 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 15 of theinvention;

[0115]FIG. 73 is a cross section schematically showing a structure of anonvolatile semiconductor memory device of an embodiment 16 of theinvention;

[0116] FIGS. 74 to 77 are schematic cross sections showing, inaccordance with the order of steps, a method of manufacturing thenonvolatile semiconductor memory device of the embodiment 16 of theinvention;

[0117] FIGS. 78 to 80 are cross sections schematically showing astructure of a nonvolatile semiconductor memory device of an embodiment17 of the invention;

[0118]FIG. 81 is a block diagram showing a structure of a conventionalflash memory;

[0119]FIG. 82 is an equivalent circuit diagram showing a schematicstructure of a memory matrix shown in FIG. 81;

[0120]FIG. 83 is a fragmentary plan showing a schematic structure in amemory cell matrix of a conventional flash memory;

[0121]FIG. 84 is a cross section taken along line D-D′ in FIG. 83;

[0122]FIG. 85 shows a write operation of a flash EEPROM utilizingchannel hot electrons;

[0123]FIG. 86 shows an erase operation utilizing an F-N tunnelphenomenon;

[0124]FIG. 87 is a cross section schematically showing a structure of aconventional nonvolatile semiconductor memory device;

[0125]FIG. 88 is a fragmentary cross section showing, on an enlargedscale, a portion S in FIG. 87;

[0126]FIG. 89 is a graph showing change of an electric field parallel toa channel in structures provided with a pocket region and not providedwith the same;

[0127]FIG. 90 shows a manner of change of a moving direction of highenergy electrons by elastic scattering;

[0128]FIG. 91 shows lateral and longitudinal electric fields of aninsulating film;

[0129]FIG. 92A is a fragmentary cross section showing, on an enlargedscale, a drain end of a conventional MOS transistor;

[0130]FIG. 92B shows change of a potential distribution in a directionvertical to a channel at the drain end of the conventional MOStransistor; and

[0131]FIG. 93 shows increase in height of a barrier of an insulatingfilm against electrons in accordance with increase of a potentialdifference at the insulating film.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0132] Embodiments of the invention will be described below withreference to the drawings.

Embodiment 1

[0133] Referring to FIG. 1, a memory transistor of a flash EEPROMincludes an n⁺ source diffusion region 12, n⁺ drain diffusion regions13, insulating films 3, floating gate electrodes 4, interlayerinsulating films 5, and control gate electrodes 6. The n⁺ sourcediffusion region 12 and n⁺ drain diffusion region 13 are formed at asurface of a p-type silicon substrate 1 with a predetermined spacebetween each other. Each floating gate electrode 4 is formed on a regionbetween n⁺ source diffusion region 12 and n⁺ drain diffusion region 13with insulating film 3 therebetween. Each control gate electrode layer 6extends on floating gate electrode 4 with interlayer insulating layer 5therebetween.

[0134] A side wall insulating layer 7 made of, e.g., a silicon oxidefilm, covers side surfaces of floating gate electrode 4 and control gateelectrode 6.

[0135] The n⁺ source diffusion region 12 and n⁺ drain diffusion region13 extend to regions in p-type silicon substrate 1 located immediatelyunder the floating gate electrode 4. There are also formed n-typeregions (HDD region) 14, each of which is in contact with and surroundscorresponding n⁺ drain diffusion region 13. Each n-type region 14 is incontact with and surrounded by a p⁺ pocket region 15. The n-type region14 and p⁺ pocket region 15 extend to regions in p-type silicon substrate1 located immediately under the floating gate electrode 4.

[0136] A memory transistor 20 is covered with an interlayer insulatinglayer 8 formed on p-type silicon substrate 1. Interlayer insulatinglayer 8 is provided with a contact hole 9 reaching a surface portion ofn⁺ source diffusion region 12. A titanium alloy film 10 and an aluminumalloy interconnection layer 11 are formed in a layered form oninterlayer insulating layer 8, and titanium alloy film 10 is in contactwith n⁺ source diffusion region 12 through contact hole 9.

[0137] Insulating film 3 is made of, e.g., a silicon oxide film, and hasa thickness of about 100 Å. Floating gate electrode 4 is made of, e.g.,doped polycrystalline silicon, and has a thickness of about 1000 Å.Interlayer insulating layer 5 is a composite film made of a siliconoxide film and a silicon nitride film, and has a whole thickness ofabout 200 Å. Control gate electrode 6 is made of, e.g., dopedpolycrystalline silicon, and has a thickness of about 2500 Å. Interlayerinsulating layer 8 is formed of a layered structure made of, e.g., a PSGor BPSG film and a silicon oxide film not doped with impurity, and has awhole thickness of about 5000 to about 15000 Å. Contact hole 9 has anopening size, e.g., of about 0.6 to 1.5 μm. Titanium alloy film 10 has athickness, e.g., of about 500 Å. Aluminum alloy interconnection layer 11has a thickness, e.g., of about 10000 Å. Titanium alloy film 10 andaluminum alloy interconnection layer 11 form a bit line.

[0138] The impurity concentration of n-type impurity region 14 must besufficiently higher than that of an LDD region used as an electric fieldrelieving layer, and must be lower than that of n⁺ drain diffusionregion 13. The impurity concentration of p⁺ pocket region 15 must behigher than that of p-type silicon substrate 1.

[0139] In this embodiment, n⁺ source diffusion region 12 has theimpurity concentration of 5 ×10²⁰cm⁻³, n⁺ drain diffusion region 13 hasthe impurity concentration of 1×10²¹cm⁻³, n-type region 14 has theimpurity concentration of ×10²⁰cm^(×3), and p⁺ pocket region 15 has theimpurity concentration of 1×10 ¹⁹cm⁻³.

[0140] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0141] Referring to FIG. 2, a well region and an element isolating oxidefilm (not shown) are formed at predetermined regions in p-type siliconsubstrate 1, and then an insulating film 3 a made of, e.g., a siliconoxide film having a thickness of about 100 Å is formed on the wholesurface. Thereafter, a first doped polycrystalline silicon layer 4 a ofabout 1000 Å in thickness is formed on insulating film 3 a, and then ispatterned into an intended configuration. An interlayer insulating layer5 a made of a composite film formed of, e.g., a silicon oxide film and asilicon nitride film and having a thickness of about 200 Å is formed onfirst doped polycrystalline silicon layer 4 a. Then, a second dopedpolycrystalline silicon layer 6 a of about 2500 Å in thickness is formedon interlayer insulating layer 5 a.

[0142] Referring to FIG. 3, a resist pattern 17 is formed at apredetermined region on second doped polycrystalline silicon layer 6 aby photolithography. Using resist pattern 17 as a mask, anisotropicetching is effected to pattern second doped polycrystalline siliconlayer 6 a, interlayer insulating layer 5 a, first doped polycrystallinesilicon layer 4 a and insulating film 3 a.

[0143] Referring to FIG. 4, the above patterning forms floating gateelectrode 4 on p-type silicon substrate 1 with insulating film 3therebetween, and also forms control gate electrode 6 on floating gateelectrode 4 with interlayer insulating layer 5 therebetween. Then,resist pattern 17 is removed.

[0144] Referring to FIG. 5, a resist pattern 18 covering a drainformation region of the memory transistor is formed by conventionalphotolithography. Using resist pattern 18 and control gate electrode 6as a mask, impurity such as arsenic (As) is ion-implanted into the mainsurface of p-type silicon substrate 1 under the conditions of about 35keV and about ×10¹⁵cm⁻². Thereby, a source region 12 a is formed. Then,resist pattern 18 is removed.

[0145] Referring to FIG. 6, a resist pattern 19 covering a sourceformation region of the memory transistor is formed by the conventionalphotolithography. Using resist pattern 19 and control gate electrode 6as a mask, impurity such as arsenic (As) is ion-implanted into the mainsurface of p-type silicon substrate 1 under the conditions of about 35keV and about 1×10¹⁶cm⁻². Thereby, a drain region 13 a is formed.

[0146] Referring to FIG. 7, using resist pattern 19 and control gateelectrode 6 as a mask, impurity such as phosphorus (P) is ion-implantedunder the conditions of about 50 keV and about 1×10¹⁵cm⁻². Thereby, ann-type region 14 a is formed under drain region 13 a.

[0147] Referring to FIG. 8, using resist pattern 19 and control gateelectrode 6 as a mask, impurity such as boron (B) is ion-implanted intothe main surface of p-type silicon substrate 1 by a tilt-angle rotaryimplanting method under the conditions of about 35 keV and about1×10¹⁴cm⁻². Thereby, a pocket region 15 a is formed at a lower portionof n-type region 14 a. Thereafter, resist pattern 19 is removed.

[0148] Referring to FIG. 9, a silicon oxide film 7 a having a thickness,e.g., of 2000 Å is formed on the whole surface. Thereafter, anisotropicRIE (Reactive Ion Etching) is effected on silicon oxide film 7 a.

[0149] Referring to FIG. 10, this etching forms side wall insulatinglayer 7 made of, e.g., a silicon oxide film and covering the sidesurfaces of floating gate electrode 4 and control gate electrode 6. Sidewall insulating layer 7 has a width or thickness W₁ of about 2000 Å.Thus, width W₁ of side wall insulating layer 7 is substantially equal toa thickness T₁ of silicon oxide film 7 a (see FIG. 9). Accordingly, bycontrolling thickness T₁ of silicon oxide film 7 a (see FIG. 9), widthW₁ of side wall insulating layer 7 can be controlled easily.

[0150] Referring to FIG. 11, a CVD (Chemical Vapor Deposition) or thelike is executed to form interlayer insulating layer 8 having athickness of about 5000 to about 15000 Å. Thereafter, a reflow method isexecuted to perform thermal treatment at a temperature of 700 to 1000°C. for flattening the surface thereof. Interlayer insulating layer 8 isformed of, e.g., a layered film made of a PSG or BPSG film and a siliconoxide film not doped with impurity. During this reflow, the source/drainregions and others are driven (diffused), so that n⁺ source diffusionregion 12, n⁺ drain diffusion region 13, p⁺ pocket region 15 and n-typeregion 14 are formed.

[0151] Referring to FIG. 12, contact hole 9 reaching n⁺ source diffusionregion 12 is formed at interlayer insulating layer 8 by conventionalphotolithography and etching techniques. Contact hole 9 has an openingsize of about 0.6 to about 1.5 μm.

[0152] Referring to FIG. 13, a step is performed to form titanium alloyfilm 10, which is made of a TiN film, has a thickness of about 500 Å,extends on interlayer insulating layer 8 and has a portion electricallyconnected to n⁺ source diffusion region 12 through contact hole 9.

[0153] Referring to FIG. 14, a sputtering method or the like is executedto form aluminum alloy film 11 of about 10000 Å in thickness on titaniumalloy film 10. Titanium alloy film 10 and aluminum alloy film 11 arepatterned by photolithography and dry etching techniques. Thereby,titanium alloy film 10 and aluminum alloy film 11 form the bit lineelectrically connected to source diffusion region 12.

[0154] The nonvolatile semiconductor memory device of this embodiment isprovided with n-type region 14, which is in contact with n⁺ draindiffusion region 13 and surrounds n⁺ drain diffusion region 13. FIG. 15shows change in a lateral electric field in accordance with change inthe impurity concentration of n-type region 14. Referring to FIG. 15,when the impurity concentration of n-type region is equal to that of aconventional LDD region, a lateral electric field generated betweenn-type region 14 (which is shown as the HDD region here) and p⁺ pocketregion 15 is substantially equal in intensity to the lateral electricfield between HDD region 14 and n⁺ drain diffusion region 13.

[0155] When the impurity concentration of HDD region 14 is higher thanthat of the LDD structure, the lateral electric field at a junctionbetween HDD region 14 and p⁺ pocket region 15 is higher than the lateralelectric field generated at the junction between HDD region 14 and n⁺drain diffusion region 13.

[0156] Owing to provision of HDD region (n-type region) 14 in thismanner, a point where the lateral electric field of insulating film 3attains the maximum intensity can be shifted toward the source diffusionregion compared with the case where the HDD region (n-type region) isnot provided as shown in FIG. 16.

[0157] The following simulation was performed with respect to change inthe lateral and longitudinal electric fields of insulating film 3 in thestructure provided with n-type region 14.

[0158] As shown in FIGS. 17 and 18, specimens were prepared for thestructure not provided with the n-type region (conventional example) andthe structure provided with the same (embodiment of the invention).

[0159] The specimen of the conventional example shown in FIG. 17 wasprepared in the following manner. After forming gate 4, arsenic (As) isimplanted into substrate 1 under the conditions of 35 keV and ×10¹⁴cm⁻²to form n⁺ drain diffusion region 13, and boron (B) is ion-implanted bythe tilt-angle rotary ion implantation with an angle of 45° with respectto the surface of substrate 1 under the conditions of 50 keV and3×10¹³cm⁻², so that p-type pocket region 15 is formed.

[0160] Meanwhile, the specimen of the example of the invention wasprepared as follows. After forming gate 4, arsenic (As) is implantedinto substrate 1 under the conditions of 35 keV and ×10¹⁴cm⁻² to form n⁺drain diffusion region 13, and phosphorus (P) is ion-implanted under theconditions of 35 keV and 1×10¹⁴cm⁻² to form n-type region 14. Further,boron (B) is ion-implanted by the tilt-angle rotary ion implantationwith an angle of 45° with respect to the surface of substrate 1 underthe conditions of 50 keV and 3×10¹³cm⁻², so that p-type pocket region 15is formed.

[0161]FIG. 19 shows a graph representing the impurity concentration atvarious positions along line A-A′ in the substrate of the conventionalexample shown in FIG. 17 as well as a graph representing thelongitudinal and lateral electric fields of the gate insulating filmcorresponding to these positions. FIG. 20 shows a graph representing theimpurity concentration at various positions along line A-A′ in thesubstrate of the example of the invention shown in FIG. 18 as well as agraph representing the longitudinal and lateral electric fields of thegate insulating film corresponding to these positions.

[0162]FIG. 21 shows graphs of FIGS. 19 and 20 in an overlapped manner.

[0163] Referring particularly to FIG. 21, thick curves represent changein the lateral and longitudinal electric fields of the specimen of theinventional example, and thin curves represent change in the lateral andlongitudinal electric fields of the conventional example. It can beunderstood also from FIG. 21 that provision of the n-type region asemployed in the inventional example shown in FIG. 18 shifts the point ofthe maximum lateral electric field of insulating film 3 toward thesource diffusion region. Owing to the shift of the point of the maximumlateral electric field toward the source diffusion region, an absolutevalue of the lateral electric field at the point of the maximum lateralelectric field in the specimen of the inventional example is smallerthan that of the conventional example.

[0164] For the respective specimens shown in FIGS. 17 and 18, injectionefficiencies (Ig/Is) were calculated with various values of gate voltagevg. The result is shown in FIG. 22. Referring to FIG. 22, it can be seenthat the injection efficiency (Ig/Is) of the structure of theinventional example (∘), which is indicated by circular marks, isconsiderably advantageous compared with the structure of theconventional example (Δ) indicated by triangular marks.

[0165] From the above result of simulation, provision of n-type region14 shown in FIG. 1 can shift the point of the maximum lateral electricfield of insulating film 3, so that the longitudinal electric field canbe reduced at the point of the maximum lateral electric field. Thisreduces the force returning electrons in insulating film 3 towardsilicon substrate 1, and reduces the height of the barrier of insulatingfilm 3 over which electrons are to be moved. Accordingly, theprobability with which high energy electrons arrive at floating gateelectrode 4 increases, and the gate current increases.

[0166] In the embodiment shown in FIG. 1, the gate current can beincreased without increasing the impurity concentration of p⁺ pocketregion 15, owing to provision of n-type region 14. Therefore, as shownin FIG. 23, it is possible to suppress the leak current between thediffusion region and the substrate, and can improve the writeefficiency.

[0167] In this structure, since the gate current is increased byimprovement of the injection efficiency, the write capability can beimproved without increasing the applied voltage. Meanwhile, whenconsideration is made based on the write capability, this structure canbe operated with a low applied voltage. Therefore, it can be understoodthat this structure is advantageous to low-voltage operating elementsand single-power-supply elements.

[0168] The structure shown in FIG. 1 will be compared with a memorytransistor having a conventional LDD structure disclosed in Y. Ohshimaet al., “PROCESS AND DEVICE TECHNOLOGIES FOR 16 Mbit EPROMs WITHLARGE-TILT-ANGLE IMPLANTED P-POCKET CELL”, IEDM 90, pp. 95-98.

[0169]FIG. 24 is a schematic cross section showing a structure of amemory transistor disclosed in the above reference. Referring to FIG.24, p-type silicon substrate 1 is provided at its surface with an n⁺⁺source diffusion region 12 as well as n-type drain regions 61 and 63spaced from n⁺⁺ source region 12 by a predetermined distance. Floatinggate electrode 4 is formed on a region between n⁺⁺ source diffusionregion 12 and n-type drain regions 61 and 63 with insulating film 3therebetween, and control gate electrode 6 is formed on floating gateelectrode 4 with interlayer insulating layer 5 therebetween. There areformed p-type pocket regions 15, each of which is in contact with andsurrounds n⁺⁺ source diffusion region 12 or n-type drain regions 61 and63. The whole surface is covered with an insulating layer 51.

[0170] In this structure, the drain region has the conventional LDDstructure formed of n⁺ region 61 and n⁺⁺ region 63. In this conventionalLDD structure, n⁺⁺ region 63 does not extend to the region immediatelyunder the floating gate electrode 4. Therefore, high energy electronsgenerated at the vicinity of the drain end are suppressed from beinginjected into the floating gate electrode 4 to some extent.

[0171] Meanwhile, in the embodiment of the invention shown in FIG. 1,not only n-type region 14 but also n⁺ drain diffusion region 13 extendto a region immediately under floating gate electrode 4. Therefore, highenergy electrons generated near the drain end are efficiently injectedinto floating gate electrode 4.

[0172] The conventional LDD structures are disclosed also in JapanesePatent Laying-Open Nos. 2-129968 (1990), 6-177399 (1994), 2-372 (1990)and 3-72682 (1991).

Embodiment 2

[0173] Referring to FIG. 25, a structure of this embodiment differs fromthe structure of the embodiment 1 shown in FIG. 1 in that it does notinclude p⁺ pocket region 15, and includes only a p-type impurity region16. The p-type impurity region 16 covers not only the periphery ofn-type region 14 but also channel region 2 and n⁺ source diffusionregion 12. The impurity concentration of p-type impurity region 16 is,for example, 5×10¹⁸cm⁻³.

[0174] Since structures other than the above are substantially the sameas those of the embodiment 1, the same or similar portions and membersbear the same reference characters and will not be described below.

[0175] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0176] Referring first to FIG. 26, the well region and element isolatingoxide film (not shown) are formed at predetermined regions of p-typesilicon substrate 1. Boron (B) is ion-implanted into the main surface ofp-type silicon substrate 1 under the conditions of about 50 keV andabout ×10¹³cm⁻². Thereby, channel dope region 16 a is formed at apredetermined depth in p-type silicon substrate 1.

[0177] Then, insulating film 3 a made of, e.g., a silicon oxide film andhaving a thickness of about 100 Å is formed on the whole surface. Firstdoped polycrystalline silicon layer 4 a of about 1000 Å in thickness isformed on insulating film 3 a. Interlayer insulating layer 5 a of about200 Å in thickness made of, e.g., a silicon oxide film and a siliconnitride film is formed on first doped polycrystalline silicon layer 4 a.Then, second doped polycrystalline silicon layer 5 a of, e.g., 2500 Å inthickness is formed on interlayer insulating layer 4 a.

[0178] Thereafter, steps similar to those of the embodiment 1 shown inFIGS. 3 and 4 are performed for manufacturing the structure of thisembodiment.

[0179] Referring to FIG. 27, resist pattern 18 is formed over the drainformation region of the memory transistor by the conventionalphotolithography. Using resist pattern 18 and control gate electrode 6as a mask, arsenic (As) is ion-implanted into the main surface of p-typesilicon substrate 1 under the conditions of about 35 keV and about5×10¹⁵cm⁻². Thereby, source region 12 a is formed at p-type siliconsubstrate 1. Thereafter, resist pattern 18 is removed.

[0180] Referring to FIG. 28, resist pattern 19 is formed over the sourceformation region of the memory transistor by the conventionalphotolithography. Using resist pattern 19 and control gate electrode 6as a mask, arsenic (As) is ion-implanted into the main surface of p-typesilicon substrate 1 under the conditions of about 35 keV and about1×10¹⁶cm⁻². Thereby, drain region 13 a is formed above channel doperegion 16 a in p-type silicon substrate 1.

[0181] Referring to FIG. 29, using resist pattern 19 and control gateelectrode 6 as a mask, phosphorus (P) is ion-implanted into the mainsurface of p-type silicon substrate 1 under the conditions of about 35keV and about 5×10¹⁵cm⁻². Thereby, n-type region 14 a is formed betweenchannel dope region 16 a and drain region 13 a.

[0182] Thereafter, the nonvolatile semiconductor memory device shown inFIG. 30 is completed through steps similar to those of the embodiment 1shown in FIGS. 8 to 14.

[0183] The nonvolatile semiconductor memory device of this embodiment isprovided with n-type region 14 covering n⁺ drain diffusion region 13similarly to the embodiment 1. Therefore, high energy electrons can beinjected into floating gate electrode 4 with a high efficiency, and thusthe gate current can be increased. Also, the leak current between thediffusion region and the substrate can be suppressed. Further, thestructure is advantageous to low-voltage operating elements andsingle-power-supply elements, similarly to the embodiment 1.

[0184] In addition to the above, p⁺ impurity region 16 covers not onlyn-type region 14 but also channel region 2 and n⁺ source diffusionregion 12. Therefore, punch through is suppressed, and a limit gatelength determined based on the off breakdown voltage can be short. Thus,the structure of this embodiment is advantageous to microscopic devicefabrication.

Embodiment 3

[0185] Referring to FIG. 31, a structure of this embodiment differs fromthat of the embodiment 1 shown in FIG. 1 in that it does not includen-type region 14 and includes p-type impurity region 16. Since n-typeregion 14 is not employed, p⁺⁺ pocket region 15 is in contact with n⁺drain diffusion region 13, and surrounds the periphery thereof. The p⁺impurity region 16 is in contact with and surrounds p⁺ pocket region 15,and covers channel region 2 and n⁺ source diffusion region 12.

[0186] The p⁺ impurity region 16 has an impurity concentration, which ishigher than that of p-type silicon substrate 1 and is lower than that ofp⁺⁺ pocket region 15.

[0187] The n⁺ drain diffusion region 13 and n⁺ source diffusion region12 have impurity concentrations of 1×10²⁰cm^(×3) or more.

[0188] Since structures other than the above are substantially the sameas those of the embodiment 1, the same or similar portions and membersbear the same reference characters and will not be described below.

[0189] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0190] Referring first to FIG. 32, the well region and element isolatingoxide film (not shown) are formed at predetermined regions of p-typesilicon substrate 1. Boron (B) is ion-implanted into the main surface ofp-type silicon substrate 1 under the conditions of about 50 keV andabout 5×10¹³cm⁻². Thereby, a channel dope region 16 a is formed at apredetermined depth in p-type silicon substrate 1. Then, an insulatingfilm 3 a made of, e.g., a silicon oxide film and having a thickness ofabout 100 Å is formed on the whole surface. First doped polycrystallinesilicon layer 4 a of about 1000 Å in thickness is formed on insulatingfilm 3 a. Interlayer insulating layer 5 a of about 200 Å in thicknessmade of, e.g., a composite film formed of a silicon oxide film and asilicon nitride film is formed on first doped polycrystalline siliconlayer 4 a. Then, second doped polycrystalline silicon layer 5 a of,e.g., 2500 Å in thickness is formed on interlayer insulating layer 4 a.

[0191] Thereafter, steps similar to those of the embodiment 1 shown inFIGS. 3 and 4 are performed for manufacturing the structure of thisembodiment.

[0192] Referring to FIG. 33, resist pattern 18 is formed over the drainformation region of the memory transistor by the conventionalphotolithography. Using resist pattern 18 and control gate electrode 6as a mask, arsenic (As) is ion-implanted into the main surface of p-typesilicon substrate 1 under the conditions of about 35 keV and about5×10¹⁵cm⁻². Thereby, source diffusion region 12 a is formed. Thereafter,resist pattern 18 is removed.

[0193] Referring to FIG. 34, resist pattern 19 is formed over the sourceformation region of the memory transistor by the conventionalphotolithography. Using resist pattern 19 and control gate electrode 6as a mask, arsenic (As) is ion-implanted into the main surface of p-typesilicon substrate 1 under the conditions of about 35 keV and about1×10¹⁶cm⁻². Thereby, drain region 13 a is formed above channel doperegion 16 a in p-type silicon substrate 1.

[0194] Referring to FIG. 35, using resist pattern 19 and control gateelectrode 6 as a mask, boron (B) is ion-implanted by tilt-angle rotaryimplantation with an angle of 45° into the main surface of p-typesilicon substrate 1 under the conditions of about 35 keV and about5×10¹³cm⁻². Thereby, p-type pocket region 15 a is formed between channeldope region 16 a and drain region 13 a.

[0195] Thereafter, the nonvolatile semiconductor memory device shown inFIG. 36 is completed through steps similar to those of the embodiment 1shown in FIGS. 9 to 14.

[0196] In the nonvolatile semiconductor memory device of thisembodiment, the injection efficiency is improved by increasing thelongitudinal electric field in the bulk, whereby the gate electrode isincreased. This will be described below more in detail.

[0197] Before this description, Poisson's Equation will be derived.

[0198] When one positive charge exists, one negative charge pairedtherewith necessarily exists. For one pair, there necessarily existsonly one line of electric force directed from the positive to thenegative. Therefore, when a certain space, e.g., of a rectangularparallelepiped is defined as shown in FIG. 37, the sum of lines ofelectric force projecting from the defined space is equal in number tothe sum of charges which are not paired with charges existing in thespace. When the charges not paired in the space are, e.g., five innumber, the lines of electric force projected from the space are five innumber.

[0199] Assuming that D represents the number of lines of electric forcesper area, sum Q of internal charges can be obtained by integration of Dalong the surface of the space. This can be represented by the followingformula:

Q=∫∫Dds

[0200] Assuming that Na represents the impurity concentration pervolume, Q can be obtained by integration of Na over the whole area inthe rectangular parallelepiped, as represented by the following formula:

Q=∫∫∫Nadv

[0201] From the above, a relationship between Na and D can berepresented as follows:

∫∫DdS=∫∫∫qNadv→aNA=(d/dx)D  (1)

[0202] As a multiplier between the electric force line density (D) andelectric field (E), there exists a dielectric constant (ε). Thedielectric constant represents a degree of induction of electric forcelines with respect to the electric field, and is defined to satisfy thefollowing formula:

D=εE

[0203] Based the above relationship, the formula (1) can be rewritteninto the following formula:

qNa=(d/dx)εE

[0204] Further, the electric field E is the quantity defined by positiondifferentiation of the potential (electric potential).

E=−(d/dx)V

[0205] From the above, Poisson's Equation can be derived as thefollowing formula (2):

qNa/ε=−(d/dx)(d/dx)V  (2)

[0206] In the strict sense of the word, the potential is different fromthe electric potential, these can be considered to be substantially thesame.

[0207]FIG. 39 shows distribution of the potential in the directionindicated by line B-B′ in the MOS (Metal Oxide Semiconductor) transistorshown in FIG. 38. The curve of potential in Si is derived by solving thePoisson's equation. The potential is represented by φ.

(qN/ε)=−(d ² φ/dx ²)  (3)

[0208] By integration of the above formula (3), the following formula(4) is derived:

−(dφ/dx)=(qN/ε)(x−x _(b))=E  (4)

[0209] The left member in the formula (4) represents the electric field,and specifically represents the quantity determined by a gradient of thecurve of the potential. When coordinates are set such that φ is given bythe ordinate and x is given by the abscissa, the gradient goes to 0 atx=x_(b). The above formula will be solve based on the conditions assumedas described above.

φ=−(qN/ε){(x ²/2)−x _(b)x}−2φ_(b)  (5)

[0210] The left member in the formula (5) represents the potential, anddetermines the curve in FIG. 40. Here, it is assumed that a relationshipof φ=−2φ_(b) with x=0 is established. Although φ_(b) is a constant whichis given as a physical quantity, x_(b) is a variable. x_(b) can becalculated as follows by substituting 0 for φin the formula (5) (φ=0)when x is x_(b) $\begin{matrix}{0 =  {{{- ( {{qN}/ɛ} )}\{ {( {x^{2}/2} ) - {x^{2}b}} \}} - {2\varphi_{b}}}arrow{x_{b}\{ {( {2{ɛ/{qN}}} )2\varphi_{b}} \}^{1/2}} } & (6)\end{matrix}$

[0211] By substituting the formula (6) for the formula (5), an intendedpotential curve in the bulk can be formulated as follows:$\begin{matrix}{\varphi = {{- ( {{qN}/ɛ} )}\{ {( {x^{2}/2} ) - {x\{ {( {2{ɛ/{qN}}} )2\varphi_{b}} \}^{1/2}} - {2\varphi_{b}}} }} \\{= {{{- ( {{{qN}/2}ɛ} )}x^{2}} - {2{x( {{qN}\quad {\varphi_{b}/ɛ}} )}^{1/2}} - {2\varphi_{b}}}}\end{matrix}$

[0212] Here, a relationship between the electric field E in the bilk andthe substrate concentration N can be represented by the followingformula which is derived from combination of the formulas (6) and (4).$\begin{matrix}{E = {( {{qN}/ɛ} )\lbrack {x - \{ {( {2{ɛ/{qN}}} )2\quad \varphi_{b}} \}^{1/2}} \rbrack}} \\{= {{( {{qN}/ɛ} )x} - {2( {{qN}\quad {\varphi_{b}/ɛ}} )^{1/2}}}}\end{matrix}$

[0213] In the above formula, N is sufficiently larger than 1, so that itis apparent that electric field E along the gate electrode direction inthe bulk increases as substrate concentration N increases.

[0214] As described above, the longitudinal electric field along thegate electrode direction in the bilk can be increased by provision of p⁺impurity region 16 and p⁺⁺ pocket region 15 which have the impurityconcentrations higher than that of p-type silicon substrate 1, as isdone in this embodiment. Thereby, the gate current can be increased, andthe write capability can be improved without increasing the appliedvoltage. Meanwhile, when consideration is made based on the writecapability, this structure can be operated with a low applied voltage.Therefore, it can be understood that this structure is advantageous tolow-voltage operating elements and single-power-supply elements.

[0215] S Since p⁺⁺ pocket region 15 having the impurity concentrationhigher than that of p-type silicon substrate 1 is arranged at the mainsurface of p-type silicon substrate 1 between n⁺ source diffusion region12 and n⁺ drain diffusion region 13, punch through can be prevented.Therefore, a limit gate length determined based on the off breakdownvoltage can be short. Thus, the structure of this embodiment isadvantageous to microscopic device fabrication.

[0216] In addition to p⁺⁺ pocket region 15, p⁺ impurity region 16 havingthe impurity concentration higher than that of p-type silicon substrate1 is arranged at the main surface of p-type silicon substrate 1 betweenn⁺ source diffusion region 12 and n⁺ drain diffusion region 13.Therefore, punch through can be prevented further effectively.

[0217] By appropriately selecting the impurity concentrations of p⁺⁺pocket region 15 and p-type impurity region 16, the threshold voltagecan be controlled while maintaining the intended limit gate length andintended write capability.

[0218] In addition to the above, by appropriately selecting the impurityconcentrations of p⁺⁺ pocket region 15 and p-type impurity region 16,the impurity concentration of p⁺⁺ pocket region 15 can be reduced whilemaintaining the intended write capability and intended thresholdvoltage. Therefore, the write capability can be improved withoutincreasing the leak current between the diffusion region and thesubstrate.

Embodiment 4

[0219] Referring to FIG. 41, a structure of this embodiment differs fromthe structure of the embodiment 3 shown in FIG. 31 in that itadditionally includes n-type region 14. The n-type region 14 is incontact with n⁺ drain diffusion region 13, and covers the periphery ofthe same. The p⁺⁺ pocket region 15 is in contact with n-type region 14,and covers the periphery of the same. The n-type region 14 has theimpurity concentration lower than that of the drain diffusion region.

[0220] Since structures other than the above are substantially the sameas those of the embodiment 3, the same or similar portions and membersbear the same reference characters and will not be described below.

[0221] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0222] Referring first to FIG. 42, the well region and element isolatingoxide film (not shown) are formed at predetermined regions of p-typesilicon substrate 1. Boron (B) is ion-implanted into the main surface ofp-type silicon substrate 1 under the conditions of about 50 keV andabout 5×10¹³cm⁻². Thereby, channel dope region 16 a is formed at p-typesilicon substrate 1. Then, insulating film 3 a made of, e.g., a siliconoxide film and having a thickness of about 100 Å is formed on the wholesurface. First doped polycrystalline silicon layer 4 a of about 1000 Åin thickness is formed on insulating film 3 a. Interlayer insulatinglayer 5 a of about 200 Å in thickness made of, e.g., a composite filmformed of a silicon oxide film and a silicon nitride film is formed onfirst doped polycrystalline silicon layer 4 a. Then, second dopedpolycrystalline silicon layer 5 a of about 2500 Å in thickness is formedon interlayer insulating layer 4 a.

[0223] Thereafter, steps similar to those of the embodiment 1 shown inFIGS. 3 and 4 are performed for manufacturing the structure of thisembodiment.

[0224] Referring to FIG. 43, resist pattern 18 is formed over the drainformation region of the memory transistor by the conventionalphotolithography. Using resist pattern 18 and control gate electrode 6as a mask, arsenic (As) is ion-implanted into the main surface of p-typesilicon substrate 1 under the conditions of about 35 keV and about5×10¹⁵cm⁻². Thereby, source region 12 a is formed above channel doperegion 16 a. Thereafter, resist pattern 18 is removed.

[0225] Referring to FIG. 44, resist pattern 19 is formed over the sourceformation region of the memory transistor by the conventionalphotolithography. Using resist pattern 19 and control gate electrode 6as a mask, arsenic (As) is ion-implanted into the main surface of p-typesilicon substrate 1 under the conditions of about 35 keV and about1×10¹⁶cm⁻². Thereby, drain region 13 a is formed above channel doperegion 16 a.

[0226] Referring to FIG. 45, using resist pattern 19 and control gateelectrode 6 as a mask, phosphorus (P) is ion-implanted into the mainsurface of p-type silicon substrate 1 under the conditions of about 35keV and about 5×10¹⁵cm⁻². Thereby, n-type region 14 a is formed betweenchannel dope region 16 a and drain region 13 a.

[0227] Referring to FIG. 46, using resist pattern 19 and control gateelectrode 6 as a mask, boron (B) is implanted by tilt-angle rotaryimplantation with an angel of 45° into the main surface of p-typesilicon substrate 1 under the conditions of about 35 keV and 5×10¹³cm⁻².Thereby, p-type region 15 a is formed between channel dope region 16 aand n-type region 14 a.

[0228] Thereafter, the nonvolatile semiconductor memory device shown inFIG. 47 is completed through steps similar to those of the embodiment 1shown in FIGS. 9 to 14.

[0229] The nonvolatile semiconductor memory device of this embodiment isprovided with n-type region 14 which is in contact with n⁺ draindiffusion region 13 and covers the periphery thereof, similarly to theembodiment 1 as shown in FIG. 41. Therefore, the lateral electric fieldof insulating film 3 can be shifted toward source diffusion region 12.Thereby, the longitudinal electric field can be reduced at the pointwhere the maximum lateral electric field generates. This reduces theforce returning electrons in insulating film 3 toward p-type siliconsubstrate 1, and also reduces a height of the insulating film barrierover which electrons are to be moved. Therefore, the probability ofarrival of high energy electrons at floating gate electrode 4 can beincreased, and the gate current can be increased.

[0230] The p⁺⁺ pocket region 15 and p⁺impurity region 16 which have theimpurity concentrations higher than that of silicon substrate 1 arearranged between n⁺ source diffusion region 12 and n⁺ drain diffusionregion 13. Since high substrate concentration is set between n⁺ draindiffusion region 13 and n⁺ source diffusion region 12, the electricfield along the gate electrode direction in the bulk can be large. Thisfurther improves the efficiency of injection of high energy electronsinto floating gate electrode 4.

[0231] In this manner, the gate current can be increased further, sothat the write capability can be improved without increasing the appliedvoltage. Meanwhile, when consideration is made based on the writecapability, this structure can be operated with a low applied voltage.Therefore, it can be understood that this structure is advantageous tolow-voltage operating elements and single-power-supply elements.

[0232] Since p⁺⁺ pocket region 15 having the impurity concentrationhigher than that of p-type silicon substrate 1 is arranged between n⁺source diffusion region 12 and n⁺ drain diffusion region 13, punchthrough can be prevented. Therefore, a limit gate length determinedbased on the off breakdown voltage can be short. Thus, the structure ofthis embodiment is advantageous to microscopic device fabrication.

[0233] In addition to p⁺⁺ pocket region 15, p-type region 16 having theimpurity concentration higher than that of p-type silicon substrate 1 isarranged between n⁺ source diffusion region 12 and n⁺ drain diffusionregion 13. Therefore, the punch through can be prevented furthereffectively.

[0234] By appropriately selecting the impurity concentrations of p⁺⁺pocket region 15 and p⁺ type impurity region 16, the threshold voltagecan be controlled while maintaining the intended limit gate length andintended write capability.

[0235] In addition to the above, by appropriately selecting the impurityconcentrations of p⁺⁺ pocket region 15 and p-type impurity region 16,the impurity concentration of p⁺⁺ pocket region 15 can be reduced whilemaintaining the intended write capability and intended thresholdvoltage. Therefore, the write capability can be improved withoutincreasing the leak current between the diffusion region and thesubstrate.

Embodiment 5

[0236] Referring to FIG. 48, a structure of this embodiment differs fromthe structure of the embodiment 1 shown in FIG. 1 in that itadditionally includes n⁺⁺ impurity region 20. The n⁺⁺ impurity region 20is formed at the surface of p-type silicon substrate 1 within n⁺ draindiffusion region 13. The n⁺⁺ impurity region 20 has the impurityconcentration higher than that of n⁺ drain region 13. The n⁺⁺ impurityregion 20 does not extend to a position immediately under floating gateelectrode 4, and extends to a position immediately under side wallinsulating layer 7.

[0237] In the above structure, n⁺ drain diffusion region 13 has animpurity concentration of 1×10²⁰cm⁻³, n-type region 14 has an impurityconcentration of 5×10¹⁹cm⁻³, and n⁺⁺ impurity region 20 has an impurityconcentration of about 1×10²¹cm⁻³.

[0238] Since structures other than the above are substantially the sameas those of the embodiment 1, the same or similar portions and membersbear the same reference characters and will not be described below.

[0239] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0240] In the method of manufacturing the structure of this embodiment,steps similar to those of the embodiment 1 shown in FIGS. 2 to 10 arefirst performed.

[0241] Referring to FIG. 49, a resist pattern 31 covering the sourceformation region of the memory transistor is formed by the conventionalphotolithography. Using resist pattern 31, control gate electrode 6 andside wall insulating layer 7 as a mask, arsenic (As) is ion-implantedinto the main surface of p-type silicon substrate 1 under the conditionsof about 35 keV and about 5×10¹⁵cm⁻².

[0242] Referring to FIG. 50, this ion-implantation forms an n⁺⁺ impurityregion 20 a on drain region 13 a. Then, resist pattern 31 is removed,and a structure shown in FIG. 51 is formed.

[0243] Thereafter, steps similar to those of the embodiment 1 shown inFIGS. 11 to 14 are performed, so that the nonvolatile semiconductormemory device shown in FIG. 52 is completed.

[0244] In the nonvolatile semiconductor memory device of thisembodiment, n⁺⁺ impurity region 20 having an impurity concentrationhigher than that of n⁺ drain impurity region 13 is formed at n⁺ draindiffusion region 13. Therefore, a parasitic resistance of n⁺ draindiffusion region 13 is reduced, the current driving capability isincreased, and thus improvement of the write capability and increase ofreading speed can be expected.

Embodiment 6

[0245] Referring to FIG. 53, a structure of this embodiment differs fromthe structure of the embodiment 1 shown in FIG. 1 in that itadditionally includes an n⁺⁺ impurity region 21. The n⁺⁺ impurity region21 is arranged at the surface of p-type silicon substrate 1 in n⁺ sourcediffusion region 12. The n⁺⁺ impurity region 21 has an impurityconcentration higher than that of n⁺ source diffusion region 12. The n⁺⁺impurity region 21 does not extend to a region immediately underfloating gate 4, and extends only to regions immediately under side wallinsulating layers 7.

[0246] The n⁺⁺ impurity region has an impurity concentration of about1×10²¹cm⁻³.

[0247] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0248] In a method of manufacturing the structure of this embodiment,steps similar to those of the embodiment 1 shown in FIGS. 2 to 10 areperformed.

[0249] Referring to FIG. 54, a resist pattern 32 covering the drainformation region of the memory transistor is formed by the conventionalphotolithography. Using resist pattern 32, control gate electrode 6 andside wall insulating layer 7 as a mask, arsenic (As) is ion-implantedinto the main surface of p-type silicon substrate 1 under the conditionsof about 35 keV and about 5×10¹⁵cm⁻².

[0250] Referring to FIG. 55, this ion-implantation forms an n⁺⁺ impurityregion 21 a on source region 12 a in p-type silicon substrate 1. Then,resist pattern 32 is removed, and a structure shown in FIG. 56 isformed.

[0251] Thereafter, steps similar to those of the embodiment 1 shown inFIGS. 11 to 14 are performed, so that the nonvolatile semiconductormemory device shown in FIG. 57 is completed.

[0252] In the nonvolatile semiconductor memory device of thisembodiment, n⁺⁺ impurity region 21 having an impurity concentrationhigher than that of n⁺ source impurity region 12 is formed at n⁺ sourcediffusion region 12. Therefore, a parasitic resistance of n⁺ sourcediffusion region 12 is reduced, the current driving capability isincreased, and thus improvement of the write capability and increase ofreading speed can be expected.

Embodiment 7

[0253] Referring to FIG. 58, a structure of this embodiment differs fromthe structure of the embodiment 1 shown in FIG. 1 in that itadditionally includes n⁺⁺ impurity regions 20 and 21. The n⁺⁺ impurityregion 20 is arranged at the surface of p-type silicon substrate 1 in n⁺drain diffusion region 13. The n⁺⁺ impurity region 20 has an impurityconcentration higher than that of n⁺ drain diffusion region 13.

[0254] The n⁺⁺ impurity region 21 is arranged at the surface of p-typesilicon substrate 1 in n⁺ source diffusion region 12. The n⁺⁺ impurityregion 21 has an impurity concentration higher than that of n⁺ sourcediffusion region 12.

[0255] The n⁺⁺ impurity regions 20 and 21 do not extend to a regionimmediately under floating gate 4, and extend only to regionsimmediately under side wall insulating layers 7.

[0256] Each of n⁺⁺ impurity regions 20 and 21 has an impurityconcentration of about 1×10²¹cm⁻³.

[0257] Since structures other than the above are substantially the sameas those of the embodiment 1, the same or similar portions and membersbear the same reference characters and will not be described below.

[0258] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0259] In the manufacturing method of this embodiment, steps similar tothose of the embodiment 1 shown in FIGS. 2 to 10 are performed.

[0260] Then, referring to FIG. 59, using control gate electrode 6 andside wall insulating layer 7 as a mask, arsenic (As) is ion-implantedinto the main surface of p-type silicon substrate 1 under the conditionsof about 35 keV and about 5×10¹⁵cm⁻². Thereby, n⁺⁺ regions 21 a and 20 aare formed on source region 12 a and drain region 13 a in p-type siliconsubstrate 1, respectively.

[0261] Thereafter, steps similar to those of the embodiment 1 shown inFIGS. 11 to 14 are performed, so that the nonvolatile semiconductormemory device shown in FIG. 60 is completed.

[0262] In the nonvolatile semiconductor memory device of thisembodiment, n⁺⁺ impurity regions 21 and 20 are arranged in n⁺ sourcediffusion region 12 and n⁺ drain diffusion region 13, respectively. Then⁺⁺ impurity regions 20 and 21 have the impurity concentrations higherthan those of n⁺ source diffusion region 12 and n⁺ drain diffusionregion 13, respectively. Therefore, parasitic resistances of n⁺ sourcediffusion region 12 and n⁺ drain diffusion region 13 are reduced,current driving capability is increased, and improvement of increase ofthe reading speed can be expected.

[0263] In the manufacturing method of this embodiment, n⁺⁺ impurityregions 20 and 21 are formed in the same ion-implanting step. Therefore,the manufacturing steps can be simplified.

Embodiment 8

[0264] Referring to FIG. 61, a structure of this embodiment differs fromthat of the embodiment 7 shown in FIG. 58 in the structure of p⁺ pocketregion 15. The p⁺ impurity region 15 forming the pocket region in thisembodiment has a depth from the surface of p-type silicon substrate 1,which is smaller that those of n⁺ drain diffusion region 13 and n⁺source diffusion region 12. The p⁺ impurity region 15 is located at aregion immediately under floating gate electrode 4, and is in contactwith n-type region 14. The p⁺ impurity region 15 has an impurityconcentration higher than that of p-type silicon substrate 1.

[0265] Since structures other than the above are substantially the sameas those of the embodiment 7 in FIG. 58, the same or similar portionsand members bear the same reference characters and will not be describedbelow.

[0266] In the nonvolatile semiconductor memory device of thisembodiment, since p⁺ impurity region 15 is shallower than n⁺ draindiffusion region 13 and n⁺ source diffusion region 12, an area ofcontact between p⁺ impurity region 15 and n-type region 14 is smallerthan that in the structure shown in FIG. 58. Therefore, a junction leakcurrent between the diffusion region and the substrate is small, so thata boost capability is increased. Since the leak current of each ofmemory cells connected to word lines is small, the sum of leak currentsof respective memory cells can be small. Therefore, increase in numberof transistors per block can be expected.

Embodiment 9

[0267] Referring to FIG. 62, a structure of this embodiment differs fromthat of the embodiment 8 shown in FIG. 61 in the structure of p⁺ pocketregion 15. The p⁺ pocket region 15 is in contact with n-type region 14,and covers the periphery thereof. The p⁺ pocket region 15 extends to aregion of p-type silicon substrate 1 located immediately under floatinggate electrode 4. The p⁺ pocket region 15 has an impurity concentrationhigher than that of p-type silicon substrate 1.

[0268] Since structures other than the above are substantially the sameas those of the embodiment 8 in FIG. 61, the same or similar portionsand members bear the same reference characters and will not be describedbelow.

[0269] In the nonvolatile semiconductor memory device of thisembodiment, since p⁺ pocket region 15 covers both of n⁺ drain diffusionregion 13 and n-type region 14, a punch through current can be reduced.Therefore, the channel length can be reduced, which allows shrinkage ofdevices.

Embodiment 10

[0270] Referring to FIG. 63, a structure of the nonvolatilesemiconductor memory device of this embodiment differs from that of theembodiment 7 shown in FIG. 58 in the structure of p⁺ impurity region 15forming the pocket region. The p⁺ impurity region 15 is formedimmediately under floating gate electrode 4 and is in contact withn-type region 14. The p⁺ impurity region 15 has a depth from the surfaceof p-type silicon substrate 1, which is substantially equal to those ofn⁺ drain diffusion region 13 and n-type region 14. The p⁺ impurityregion 15 has an impurity concentration higher than that of p-typesilicon substrate 1.

[0271] Since structures other than the above are substantially the sameas those of the embodiment 7 shown in FIG. 58, the same or similarportions and members bear the same reference characters and will not bedescribed below.

[0272] In the nonvolatile semiconductor memory device of thisembodiment, p⁺ impurity region 15 has a relatively small depthsubstantially equal to that of n⁺ drain diffusion region 13 or n-typeregion 14. Therefore, an area of contact between n-type region 14 and p⁺impurity region 15 can be smaller than that in the structure shown inFIG. 62. Accordingly, a junction leak current between the diffusionregion and the substrate can be small, and thus improvement of the boostcapability and increase in number of transistors per block can beexpected.

[0273] Since p⁺ impurity region 15 has a depth similar to that of n⁺drain diffusion region 13, it has a portion which covers n⁺ draindiffusion region 13 and is located deeper than that in the structureshown in FIG. 61. Thereby, a punch through current can be reduced.Accordingly, the channel length can be reduced, which allows shrinkageof the device.

Embodiment 11

[0274] Referring to FIG. 64, a structure of this embodiment differs fromthe structure of the embodiment 1 shown in FIG. 1 in that itadditionally includes n-type impurity region 22. The n-type impurityregion 22 is in contact with n+ source diffusion region 12, and coversthe periphery thereof. The n-type region 22 has an impurityconcentration higher than that of n⁺ source diffusion region 12. Forexample, n⁺ source diffusion region 12 has an impurity concentration of1×10²⁰cm⁻³, in which case n-type region 22 has an impurity concentrationin a range from 1×10¹⁸cm⁻³ to 8×10¹⁹cm⁻³.

[0275] Since structures other than the above are substantially the sameas those of the embodiment 1 shown in FIG. 1, the same or similarportions and members bear the same reference characters and will not bedescribed below.

[0276] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0277] In the manufacturing method of this embodiment, steps similar tothose of the embodiment 1 shown in FIGS. 2 to 5 are first performed.

[0278] Referring to FIG. 65, using resist pattern 19 and control gateelectrode 6 as a mask, phosphorus (P) is ion-implanted into the mainsurface of p-type silicon substrate 1 under the conditions of about 50keV and about 1×10¹³cm⁻². This forms an n-type region 22 a under sourceregion 12 a. Thereafter, resist pattern 19 is removed.

[0279] Then, steps similar to those of the embodiment 1 shown in FIGS. 6to 14 are performed, whereby the nonvolatile semiconductor memory deviceshown in FIG. 66 is completed.

[0280] Since the nonvolatile semiconductor memory device of thisembodiment includes n-type region 22 covering n⁺ source diffusion region12, this promotes extension of the depletion layer at the source sideand thus increases the source breakdown voltage. For example, therefore,a high voltage can be applied to the source when erasing (removal ofelectrons from floating gate electrode 4) is performed at the sourceside with the F-N tunneling current.

Embodiment 12

[0281] Referring to FIG. 67, a structure of this embodiment differs fromthat of the embodiment 11 shown in FIG. 64 in that the depth of junctionbetween n⁺ source diffusion region 12 and n⁺drain diffusion region 13 aswell as the impurity concentration. More specifically, a depth of n⁺drain diffusion region 13 from the surface of p-type silicon substrate 1is larger than that of n⁺ source diffusion region 12.

[0282] The n⁺ source diffusion region 12 may have a depth from thesurface of p-type silicon substrate 1, which is larger than that of n⁺drain diffusion region 13.

[0283] The n⁺ source diffusion region 12 and n⁺ drain diffusion region13 may have different impurity concentrations.

[0284] Since structures other than the above are substantially the sameas those of the embodiment 11 shown in FIG. 64, the same or similarportions and members bear the same reference characters and will not bedescribed below.

Embodiment 13

[0285] Referring to FIG. 68, a structure of this embodiment differs fromthe structure of the embodiment 11 shown in FIG. 64 in the depth ofjunction between n-type region 22 at the source side and n-type region14 at the drain side, or in the impurity concentration. Morespecifically, a depth of n-type impurity region 22 at the source sidefrom the surface of p-type silicon substrate 1 is larger than that ofn-type impurity region 14 at the drain side.

[0286] The n-type region 14 at the drain side may have a depth from thesurface of p-type silicon substrate 1, which is larger than that ofn-type region 22 at the source side.

[0287] The n-type impurity region 22 at the source side and n-typeregion 14 at the drain side may have different impurity concentrations.

[0288] Since structures other than the above are substantially the sameas those of the embodiment 11 shown in FIG. 64, the same or similarportions and members bear the same reference characters and will not bedescribed below.

[0289] In the nonvolatile semiconductor memory device of thisembodiment, implantation may be effect on n-type region 22 at the sourceside under the conditions different from those under which implantationis effected on n-type region 14 at the drain side, whereby the breakdownvoltage at the source diffusion region can be improved more effectivelythan the embodiment 11 while maintaining the improved write efficiency(depending on conditions for forming n-type region 13).

Embodiment 14

[0290] Referring to FIG. 69, a structure of this embodiment differs fromthat of the embodiment 2 shown in FIG. 25 in the structure of p⁺impurity region 16. The p⁺ impurity region 16 is formed only at a regionimmediately under floating gate electrode 4 to cover channel region 2,and is in contact with n-type region 14 and n⁺ source diffusion region12 only in this region. The p⁺ impurity region 16 has an impurityconcentration higher than that of p-type silicon substrate 1.

[0291] Since structures other than the above are substantially the sameas those of the embodiment 2 shown in FIG. 25, the same or similarportions and members bear the same reference characters and will not bedescribed below.

[0292] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0293] Referring to FIG. 70, a resist pattern 33 having a hole patternat the floating gate electrode formation region is formed on p-typesilicon substrate 1 by the conventional photolithography. Using resistpattern 33 as a mask, boron (B) is ion-implanted into a regionimmediately under the floating gate electrode formation region in p-typesilicon substrate 1 under the conditions of about 80 keV and about5×10¹²cm⁻². Thereby, p⁺ region 16 a is formed at a position immediatelyunder the floating gate electrode formation region in p-type siliconsubstrate 1.

[0294] Thereafter, steps similar to those of the embodiment 2 areperformed so that the nonvolatile semiconductor memory device shown inFIG. 71 is completed.

[0295] In the nonvolatile semiconductor memory device of thisembodiment, since p⁺ impurity region 16 is formed only at the regionimmediately under floating gate electrode 4, it is in contact withn-type region 14 and n⁺ source diffusion region 12 only in this region.Therefore, capacitances of the diffusion regions in the source and drainare reduced. Accordingly, increase of the reading speed can be expected.

Embodiment 15

[0296] Referring to FIG. 72, a structure of the nonvolatilesemiconductor memory device of this embodiment differs from that of theembodiment 4 shown in FIG. 41 in the structure of p⁺ impurity region 16.The p⁺ impurity region 16 is formed only at a region immediately underfloating gate electrode 4, and is in contact with p⁺⁺ pocket region 15and n⁺ source diffusion region 12 only in this region. The p⁺ impurityregion 16 has an impurity concentration which is higher than that ofp-type silicon substrate 1 and is lower than that of p⁺⁺ pocket region15.

[0297] According to the nonvolatile semiconductor memory device of thisembodiment, capacitances of diffusion regions in the source and draincan be reduced similarly to the embodiment 14, and thus increase of thereading speed can be expected.

Embodiment 16

[0298] Referring to FIG. 73, a structure of this embodiment differs fromthat of the embodiment 3 shown in FIG. 31 in the structure of p⁺impurity region 16. The p⁺ impurity region 16 is formed only at a regionimmediately under floating gate electrode 4, and is in contact withn-type region 15 and n⁺ source diffusion region 12 only in this region.The p⁺impurity region 16 has an impurity concentration which is higherthan that of p-type silicon substrate 1 and is lower than that of p⁺⁺pocket region 15.

[0299] Since structures other than the above are substantially the sameas those of the embodiment 3 shown in FIG. 31, the same or similarportions and members bear the same reference characters and will not bedescribed below.

[0300] A method of manufacturing the nonvolatile semiconductor memorydevice of this embodiment will be described below.

[0301] Referring to FIG. 74, boron (B) is ion-implanted into the wholesurface of p-type silicon substrate 1 under the conditions of about 80keV and about 5×10¹²cm⁻². Thereby, p-type region 16 a is formed at apredetermined position in p-type silicon substrate 1.

[0302] In the manufacturing method of this embodiment, steps similar tothose of the embodiment 1 shown in FIGS. 2 to 4 are then executed.Thereafter, resist pattern 17 shown in FIG. 4 is removed to form astructure shown in FIG. 75.

[0303] Referring to FIG. 76, impurity exhibiting the polarity oppositeto that of boron is implanted in accordance with the range of boronimplanted in the step in FIG. 74, using floating gate electrode 6 as amask. Thereby, p-type region is canceled at the region not covered withfloating gate electrode 4. Thus, p-type impurity region 16 a remainsonly at the region immediately under the floating gate electrode 4.Thereafter, steps similar to those of the embodiment 3 are executed, sothat the nonvolatile semiconductor memory device shown in FIG. 77 iscompleted.

[0304] According to the nonvolatile semiconductor memory device of thisembodiment, capacitances of diffusion regions in the source and drainare reduced similarly to the embodiment 14, and thus increase of thereading speed can be expected.

[0305] The manufacturing method of the embodiment 14can be applied tothe embodiments 15 and 16, and the manufacturing method of theembodiment 16 can be applied to the embodiments 14 and 15.

Embodiment 17

[0306]FIGS. 78, 79 and 80 are cross sections schematically showingstructures of the nonvolatile semiconductor memory devices of theembodiment 17 which correspond to improvements of the structures of theembodiments 14 to 16, respectively.

[0307] More specifically, the structures shown in FIGS. 78 to 80correspond to the structures of the embodiments 14 to 16 shown in FIGS.69, 72 and 73, respectively, except for that p⁺ impurity region 16 has adepth from the surface of p-type silicon substrate 1 which is smallerthan those of n⁺ source diffusion region 12 and n⁺ drain diffusionregion 13. The p⁺ impurity region 16 has an impurity concentrationhigher than that of p-type silicon substrate 1.

[0308] In the structures of FIGS. 78 to 80, as described above, p⁺impurity region 16 is shallower than those in the structures of theembodiments 14 to 16, whereby it is possible to prevent variation of thethreshold voltage which may be caused by variation of the substratepotential. Therefore, it is possible to suppress variation of an unfixedpotential of a terminal in an open state.

[0309] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A nonvolatile semiconductor memory deviceallowing electrical erasing and writing of data comprising: asemiconductor substrate of a first conductivity type having a mainsurface; a charge accumulating electrode layer formed on the mainsurface of said semiconductor substrate with a first insulating filmtherebetween; a control electrode layer formed on said chargeaccumulating electrode layer with a second insulating film therebetween;a pair of source/drain regions of a second conductivity type formed atthe main surface of said semiconductor substrate and located at oppositesides of a region of said semiconductor substrate located under saidcharge accumulating electrode layer; said drain region extending to aregion of said semiconductor substrate located immediately under saidcharge accumulating electrode layer; a first impurity region of thesecond conductivity type located to be in contact with said drain regionat the main surface of said semiconductor substrate located immediatelyunder said charge accumulating electrode layer, and having an impurityconcentration lower than that of said drain region; and a secondimpurity region of the first conductivity type being in contact withsaid first impurity region at the main surface of said semiconductorsubstrate located immediately under said charge accumulating electrodelayer, and having an impurity concentration higher than that of saidsemiconductor substrate.
 2. The nonvolatile semiconductor memory deviceaccording to claim 1, wherein said second impurity region is spaced fromsaid source region by a distance.
 3. The nonvolatile semiconductormemory device according to claim 2, wherein said first impurity regioncovers the periphery of said drain region while being in contact withsaid drain region.
 4. The nonvolatile semiconductor memory deviceaccording to claim 2, further comprising a third impurity region of thefirst conductivity type covering peripheries of said source region andsaid second impurity region while being in contact with said sourceregion and said second impurity region, and having an impurityconcentration higher than that of said semiconductor substrate and lowerthan that of said second impurity region.
 5. The nonvolatilesemiconductor memory device according to claim 2, further comprising athird impurity region of the second conductivity type formed in at leastone of said drain region and said source region having an impurityconcentration higher than that of said drain region and said sourceregion.
 6. The nonvolatile semiconductor memory device according toclaim 2, wherein a depth of said second impurity region from the mainsurface of said semiconductor substrate is smaller than that of saidfirst impurity region.
 7. The nonvolatile semiconductor memory deviceaccording to claim 2, further comprising a third impurity regioncovering a periphery of said source region while being in contact withsaid source region, extending to a region of said semiconductorsubstrate immediately under said charge accumulating electrode layer,and having an impurity concentration lower than that of said sourceregion.
 8. The nonvolatile semiconductor memory device according toclaim 7, wherein said source region and said drain region have differentdepths from the main surface of said semiconductor substrate.
 9. Thenonvolatile semiconductor memory device according to claim 7, whereinsaid source region and said drain region have different impurityconcentrations.
 10. The nonvolatile semiconductor memory deviceaccording to claim 7, wherein said third impurity region and said drainregion have different depths from the main surface of said semiconductorsubstrate.
 11. The nonvolatile semiconductor memory device according toclaim 7, wherein said third impurity region and said drain region havedifferent impurity concentrations.
 12. The nonvolatile semiconductormemory device according to claim 1, wherein said second impurity regionis in contact with said source region at the main surface of saidsemiconductor substrate directly below said charge accumulatingelectrode layer.
 13. The nonvolatile semiconductor memory deviceaccording to claim 12, wherein said device further comprises a thirdimpurity region of the first conductivity type covering said firstimpurity region while being in contact with said first impurity region,and having an impurity concentration lower than that of saidsemiconductor substrate, and said third impurity region exists betweensaid second impurity region and said first impurity region.
 14. Anonvolatile semiconductor memory device allowing electrical erasing andwriting of data comprising: a semiconductor substrate of a firstconductivity type having a main surface; a charge accumulating electrodelayer formed on the main surface of said semiconductor substrate with afirst insulating film therebetween; a control electrode layer formed onsaid charge accumulating electrode layer with a second insulating filmtherebetween; a pair of source/drain regions of a second conductivitytype formed at the main surface of said semiconductor substrate, andlocated at opposite sides of a region of said semiconductor substratelocated under said charge accumulating electrode layer; said drainregion extending to a region of said semiconductor substrate locatedimmediately under said charge accumulating electrode layer, andcontaining impurity at a concentration of 1×10²⁰cm⁻³ or more; a firstimpurity region covering a periphery of said drain region while being incontact with said drain region, and having an impurity concentrationlarger than that of said semiconductor substrate; and a second impurityregion of the first conductivity type formed to be in contact with saidsource region and said first impurity region at a region of saidsemiconductor substrate located immediately under said chargeaccumulating electrode layer, and having an impurity concentrationhigher than that of said semiconductor substrate and lower than that ofsaid first impurity region.
 15. The nonvolatile semiconductor memorydevice according to claim 14, wherein a depth of said second impurityregion from the main surface of said semiconductor substrate is smallerthan that of said source/drain regions.
 16. The nonvolatilesemiconductor memory device according to claim 14, wherein said secondimpurity region covers peripheries of said source region and said firstimpurity region while it is in contact with said source region and saidfirst impurity region.
 17. The nonvolatile semiconductor memory deviceaccording to claim 1, wherein said first impurity region is in contactwith and surrounding said drain region, and said second impurity regioncovers peripheries of said source region and said first impurity region.18. A method of manufacturing a nonvolatile semiconductor memory deviceallowing electrical erasing and writing of data comprising the steps of:forming a charge accumulating electrode layer on a main surface of asemiconductor substrate of a first conductivity type with a firstinsulating layer therebetween, and a control electrode layer on saidcharge accumulating electrode layer with a second insulating filmtherebetween; forming a pair of source/drain regions of a secondconductivity type at the main surface of said semiconductor substrate,said pair of source/drain regions being located at opposite sides of aregion of said semiconductor substrate located immediately under saidcharge accumulating electrode layer; said drain region extending to aregion of said semiconductor substrate located immediately under saidcharge accumulating electrode layer; forming a first impurity region ofthe second conductivity type to be in contact with said drain region andto have an impurity concentration lower than that of said drain regionat the main surface of said semiconductor substrate located immediatelyunder said charge accumulating electrode layer; and forming a secondimpurity region of the first conductivity type to be in contact withsaid first impurity region and to have an impurity concentration higherthan that of said semiconductor substrate at the main surface of saidsemiconductor substrate located immediately under said chargeaccumulating electrode layer.
 19. The method of manufacturing thenonvolatile semiconductor memory device according to claim 18, whereinsaid step of forming said source region includes the step of implantingimpurity of the second conductivity type with a first mask disposed on adrain formation region in said semiconductor substrate, said step offorming said drain region includes the step of implanting impurity ofthe second conductivity type with a second mask disposed on a sourceformation region in said semiconductor substrate, said step of formingsaid first impurity region includes the step of implanting impurity ofthe second conductivity type using said second mask, and said step offorming said second impurity region includes the step of implantingimpurity of the first conductivity type in a direction tilted withrespect to the main surface of said semiconductor substrate using saidsecond mask.
 20. The method of manufacturing the nonvolatilesemiconductor memory device according to claim 18, wherein said methodfurther comprises the step of forming a third impurity region of thefirst conductivity type surrounding peripheries of said source regionand said second impurity region while being in contact with said sourceregion and said second impurity region, and having an impurityconcentration higher than that of said semiconductor substrate and lowerthan that of said second impurity region, and said step of forming saidthird impurity region includes the step of implanting impurity of thefirst conductivity type into said semiconductor substrate before formingsaid charge accumulating electrode layer and said control electrodelayer.
 21. The method of manufacturing the nonvolatile semiconductormemory device according to claim 18, further comprising the steps of:forming a side wall insulating layer covering side walls of said chargeaccumulating electrode layer and said control electrode layer, forming athird impurity region of the first conductivity type in said drainregion, said third impurity region having an impurity concentrationhigher than that of said drain region, and forming a fourth impurityregion of the second conductivity type in said source region, saidfourth impurity region having an impurity concentration higher than thatof said source region, wherein said steps of forming said third andfourth impurity regions include the steps of implanting impurity of thesecond conductivity type into the main surface of said semiconductorsubstrate using said side wall insulating layer as a mask.
 22. Themethod of manufacturing the nonvolatile semiconductor memory deviceaccording to claim 18, wherein said second impurity region is formedonly at a region of said semiconductor substrate immediately under saidcharge accumulating electrode layer and is in contact with portions ofsaid source region and said first impurity region located immediatelyunder said charge accumulating electrode layer, and said step of formingsaid second impurity region includes the step of selectively implantingimpurity of the first conductivity type only into a region of saidsemiconductor substrate immediately under said charge accumulatingelectrode layer before formation of said charge accumulating electrodelayer and said control electrode layer.
 23. The method of manufacturingthe nonvolatile semiconductor memory device according to claim 18,wherein said second impurity region is formed to be in contact withportions of said source region and said first impurity region locatedimmediately under said charge accumulating electrode layer only at aregion of said semiconductor substrate immediately under said chargeaccumulating electrode layer, and said step of forming said secondimpurity region includes the steps of: implanting impurity of the firstconductivity type into the whole surface of said semiconductor substratebefore formation of said charge accumulating electrode layer and saidcontrol electrode layer, and implanting impurity of the secondconductivity type into a region other than a region of saidsemiconductor substrate immediately under said charge accumulatingelectrode layer, using said charge accumulating electrode layer and saidcontrol electrode layer as a mask.
 24. A method of manufacturing anonvolatile semiconductor memory device allowing electrical erasing andwriting of data comprising the steps of: forming a charge accumulatingelectrode layer on a main surface of a semiconductor substrate of afirst conductivity type with a first insulating layer therebetween, anda control electrode layer on said charge accumulating electrode layerwith a second insulating film therebetween; forming a pair ofsource/drain regions of a second conductivity type at the main surfaceof said semiconductor substrate, said pair of source/drain regions beinglocated at opposite sides of a region of said semiconductor substratelocated immediately under said charge accumulating electrode layer; saiddrain region extending to a region of said semiconductor substratelocated immediately under said charge accumulating electrode layer;forming a first impurity region of the second conductivity type at themain surface of said semiconductor substrate located immediately undersaid charge accumulating electrode layer, said first impurity regionbeing in contact with said drain region and having an impurityconcentration lower than that of said drain region; and forming a secondimpurity region of the first conductivity type to be in contact withsaid source region and said first impurity region and to have animpurity concentration higher than that of said semiconductor substrateat a region of said semiconductor substrate located immediately undersaid charge accumulating electrode layer.
 25. The method ofmanufacturing the nonvolatile semiconductor memory device according toclaim 24, wherein said step of forming said second impurity regionincludes the step of implanting impurity of the first conductivity intothe main surface of said semiconductor substrate before forming saidcharge accumulating electrode layer and said control electrode layer,said step of forming said source region includes the step of implantingimpurity of the second conductivity type with a first mask disposed on adrain formation region in said semiconductor substrate, said step offorming said drain region includes the step of implanting impurity ofthe second conductivity type with a second mask disposed on a sourceformation region in said semiconductor substrate, and said step offorming said first impurity region includes the step of implantingimpurity of the second conductivity type using said second mask.
 26. Amethod of manufacturing a nonvolatile semiconductor memory deviceallowing electrical erasing and writing of data comprising the steps of:forming a charge accumulating electrode layer on a main surface of asemiconductor substrate of a first conductivity type with a firstinsulating layer therebetween, and a control electrode layer on saidcharge accumulating electrode layer with a second insulating filmtherebetween; forming a pair of source/drain regions of a secondconductivity type at the main surface of said semiconductor substrate,said pair of source/drain regions being located at opposite sides of aregion of said semiconductor substrate located immediately under saidcharge accumulating electrode layer; said drain region extending to aregion of said semiconductor substrate located immediately under saidcharge accumulating electrode layer, and having an impurityconcentration of 1×10²⁰cm⁻³ 3 or more; forming a first impurity regionof the first conductivity type covering said drain region while being incontact with said drain region and having an impurity concentrationhigher than that of said semiconductor substrate; and forming a secondimpurity region of the first conductivity type to be in contact withsaid source region and said first impurity region and to have animpurity concentration higher than that of said semiconductor substrateand lower than that of said first impurity region at a region of saidsemiconductor substrate located immediately under said chargeaccumulating electrode layer.
 27. The method of manufacturing thenonvolatile semiconductor memory device according to claim 30, whereinsaid step of forming said second impurity region includes the step ofimplanting impurity of the first conductivity type into the main surfaceof said semiconductor substrate before forming said charge accumulatingelectrode layer and said control electrode layer, said step of formingsaid source region includes the step of implanting impurity of thesecond conductivity type with a first mask disposed on a drain formationregion in said semiconductor substrate, said step of forming said drainregion includes the step of implanting impurity of the secondconductivity type with a second mask disposed on a source formationregion in said semiconductor substrate, and said step of forming saidfirst impurity region includes the step of implanting impurity of thefirst conductivity type in a direction tilted with respect to the mainsurface of said semiconductor substrate using said second mask.